Apple Mac Pro 6,1 - ssvb/tinymembench GitHub Wiki
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 3860.6 MB/s (5.3%)
C copy backwards (32 byte blocks) : 4028.4 MB/s (6.3%)
C copy backwards (64 byte blocks) : 3902.1 MB/s (6.8%)
C copy : 4065.5 MB/s (6.9%)
C copy prefetched (32 bytes step) : 6295.5 MB/s (16.2%)
C copy prefetched (64 bytes step) : 4329.4 MB/s (9.4%)
C 2-pass copy : 3449.8 MB/s (7.1%)
C 2-pass copy prefetched (32 bytes step) : 3271.7 MB/s (5.5%)
C 2-pass copy prefetched (64 bytes step) : 3419.9 MB/s (7.8%)
C fill : 5511.5 MB/s (1.1%)
C fill (shuffle within 16 byte blocks) : 8326.0 MB/s (9.6%)
C fill (shuffle within 32 byte blocks) : 7391.9 MB/s (10.8%)
C fill (shuffle within 64 byte blocks) : 6617.1 MB/s (5.9%)
---
standard memcpy : 4775.1 MB/s (16.1%)
standard memset : 4586.8 MB/s (4.2%)
---
MOVSB copy : 3845.2 MB/s (4.5%)
MOVSD copy : 5852.8 MB/s (13.2%)
SSE2 copy : 3132.1 MB/s (0.2%)
SSE2 nontemporal copy : 2612.9 MB/s
SSE2 copy prefetched (32 bytes step) : 3382.3 MB/s (4.2%)
SSE2 copy prefetched (64 bytes step) : 4049.7 MB/s (10.2%)
SSE2 nontemporal copy prefetched (32 bytes step) : 3986.5 MB/s (15.2%)
SSE2 nontemporal copy prefetched (64 bytes step) : 6015.5 MB/s (18.1%)
SSE2 2-pass copy : 2964.7 MB/s (0.1%)
SSE2 2-pass copy prefetched (32 bytes step) : 4083.2 MB/s (9.6%)
SSE2 2-pass copy prefetched (64 bytes step) : 3000.7 MB/s (1.7%)
SSE2 2-pass nontemporal copy : 1182.8 MB/s (2.3%)
SSE2 fill : 9262.6 MB/s (12.9%)
SSE2 nontemporal fill : 4116.3 MB/s (0.8%)
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
MOVSD copy (from framebuffer) : 3358.7 MB/s
MOVSD 2-pass copy (from framebuffer) : 3422.0 MB/s (9.7%)
SSE2 copy (from framebuffer) : 3485.6 MB/s (4.4%)
SSE2 2-pass copy (from framebuffer) : 2826.1 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 11.3 ns / 17.5 ns
4096 : 10.9 ns / 17.5 ns
8192 : 6.4 ns / 0.7 ns
16384 : 0.1 ns / 0.0 ns
32768 : 10.9 ns / 4.1 ns
65536 : 14.2 ns / 9.9 ns
131072 : 15.4 ns / 22.5 ns
262144 : 16.7 ns / 23.5 ns
524288 : 12.4 ns / 12.8 ns
1048576 : 12.5 ns / 15.4 ns
2097152 : 14.4 ns / 16.5 ns
4194304 : 16.8 ns / 19.9 ns
8388608 : 19.5 ns / 33.0 ns
16777216 : 23.2 ns / 77.0 ns
33554432 : 75.9 ns / 103.2 ns
67108864 : 106.2 ns / 135.1 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 9.0 ns / 14.3 ns
2048 : 9.0 ns / 10.7 ns
4096 : 9.0 ns / 14.3 ns
8192 : 0.3 ns / 0.4 ns
16384 : 9.0 ns / 14.3 ns
32768 : 9.0 ns / 14.3 ns
65536 : 11.7 ns / 13.3 ns
131072 : 13.0 ns / 18.9 ns
262144 : 10.9 ns / 16.5 ns
524288 : 7.0 ns / 10.1 ns
1048576 : 9.9 ns / 12.8 ns
2097152 : 11.5 ns / 13.6 ns
4194304 : 27.2 ns / 28.4 ns
8388608 : 33.7 ns / 14.1 ns
16777216 : 46.4 ns / 59.9 ns
33554432 : 36.2 ns / 43.7 ns
67108864 : 55.1 ns / 69.1 ns