Allwinner A31 - ssvb/tinymembench GitHub Wiki

tinymembench v0.2.9 (simple benchmark for memory throughput and latency)

==========================================================================
== Memory bandwidth tests                                               ==
==                                                                      ==
== Note 1: 1MB = 1000000 bytes                                          ==
== Note 2: Results for 'copy' tests show how many bytes can be          ==
==         copied per second (adding together read and writen           ==
==         bytes would have provided twice higher numbers)              ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
==         to first fetch data into it, and only then write it to the   ==
==         destination (source -> L1 cache, L1 cache -> destination)    ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in    ==
==         brackets                                                     ==
==========================================================================

 C copy backwards                                     :    149.1 MB/s (0.8%)
 C copy                                               :    570.3 MB/s
 C copy prefetched (32 bytes step)                    :    612.2 MB/s
 C copy prefetched (64 bytes step)                    :    612.3 MB/s
 C 2-pass copy                                        :    495.5 MB/s
 C 2-pass copy prefetched (32 bytes step)             :    533.9 MB/s
 C 2-pass copy prefetched (64 bytes step)             :    533.8 MB/s
 C fill                                               :   1959.1 MB/s
 ---
 standard memcpy                                      :    626.8 MB/s
 standard memset                                      :   1931.8 MB/s (0.1%)
 ---
 NEON read                                            :    691.0 MB/s
 NEON read prefetched (32 bytes step)                 :    776.2 MB/s
 NEON read prefetched (64 bytes step)                 :    777.4 MB/s
 NEON copy                                            :    572.6 MB/s
 NEON copy prefetched (32 bytes step)                 :    558.1 MB/s
 NEON copy prefetched (64 bytes step)                 :    661.7 MB/s
 NEON unrolled copy                                   :    577.7 MB/s
 NEON unrolled copy prefetched (32 bytes step)        :    597.5 MB/s
 NEON unrolled copy prefetched (64 bytes step)        :    632.1 MB/s
 NEON copy backwards                                  :    560.8 MB/s
 NEON copy backwards prefetched (32 bytes step)       :    534.6 MB/s
 NEON copy backwards prefetched (64 bytes step)       :    653.1 MB/s
 NEON 2-pass copy                                     :    514.5 MB/s
 NEON 2-pass copy prefetched (32 bytes step)          :    569.6 MB/s
 NEON 2-pass copy prefetched (64 bytes step)          :    550.5 MB/s
 NEON unrolled 2-pass copy                            :    475.4 MB/s (0.4%)
 NEON unrolled 2-pass copy prefetched (32 bytes step) :    479.4 MB/s
 NEON unrolled 2-pass copy prefetched (64 bytes step) :    502.8 MB/s
 NEON fill                                            :   1965.5 MB/s
 NEON fill backwards                                  :   1987.4 MB/s
 ARM fill (STRD)                                      :   1924.7 MB/s
 ARM fill (STM with 8 registers)                      :   1962.4 MB/s
 ARM fill (STM with 4 registers)                      :   1950.3 MB/s
 ARM copy prefetched (incr pld)                       :    637.9 MB/s
 ARM copy prefetched (wrap pld)                       :    548.4 MB/s
 ARM 2-pass copy prefetched (incr pld)                :    546.1 MB/s
 ARM 2-pass copy prefetched (wrap pld)                :    517.5 MB/s

==========================================================================
== Memory latency test                                                  ==
==                                                                      ==
== Average time is measured for random memory accesses in the buffers   ==
== of different sizes. The larger is the buffer, the more significant   ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM      ==
== accesses. For extremely large buffer sizes we are expecting to see   ==
== page table walk with total 3 requests to SDRAM for almost every      ==
== memory access (though 64MiB is not large enough to experience this   ==
== effect to its fullest).                                              ==
==                                                                      ==
== Note 1: All the numbers are representing extra time, which needs to  ==
==         be added to L1 cache latency. The cycle timings for L1 cache ==
==         latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
==         two independent memory accesses at a time. In the case if    ==
==         the memory subsystem can't handle multiple outstanding       ==
==         requests, dual random read has the same timings as two       ==
==         single reads performed one after another.                    ==
==========================================================================

block size : read access time (single random read / dual random read)
         2 :    0.0 ns  /     0.0 ns 
         4 :    0.0 ns  /     0.0 ns 
         8 :    0.0 ns  /     0.0 ns 
        16 :    0.0 ns  /     0.0 ns 
        32 :    0.0 ns  /     0.0 ns 
        64 :    0.0 ns  /     0.0 ns 
       128 :    0.0 ns  /     0.0 ns 
       256 :    0.0 ns  /     0.0 ns 
       512 :    0.0 ns  /     0.0 ns 
      1024 :    0.0 ns  /     0.0 ns 
      2048 :    0.0 ns  /     0.0 ns 
      4096 :    0.0 ns  /     0.0 ns 
      8192 :    0.0 ns  /     0.0 ns 
     16384 :    0.0 ns  /     0.0 ns 
     32768 :    0.0 ns  /     0.0 ns 
     65536 :    6.2 ns  /    10.8 ns 
    131072 :    9.6 ns  /    15.1 ns 
    262144 :   11.2 ns  /    16.8 ns 
    524288 :   12.1 ns  /    17.4 ns 
   1048576 :   37.5 ns  /    65.8 ns 
   2097152 :  164.9 ns  /   258.0 ns 
   4194304 :  243.2 ns  /   334.7 ns 
   8388608 :  284.4 ns  /   364.7 ns 
  16777216 :  307.6 ns  /   382.0 ns 
  33554432 :  324.2 ns  /   400.1 ns 
  67108864 :  340.2 ns  /   423.9 ns 
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