AMD Ryzen 5 2600 Six Core Processor - ssvb/tinymembench GitHub Wiki
AMD Ryzen 5 2600 @ 3.4 GHz (turbo boost disabled)
4×16GB DDR4 2666MHz 15-17-17-36
$ lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 12
On-line CPU(s) list: 0-11
Thread(s) per core: 2
Core(s) per socket: 6
Socket(s): 1
NUMA node(s): 1
Vendor ID: AuthenticAMD
CPU family: 23
Model: 8
Model name: AMD Ryzen 5 2600 Six-Core Processor
Stepping: 2
CPU MHz: 2873.901
BogoMIPS: 6786.29
Virtualization: AMD-V
L1d cache: 32K
L1i cache: 64K
L2 cache: 512K
L3 cache: 8192K
NUMA node0 CPU(s): 0-11
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx hw_pstate sme ssbd ibpb vmmcall fsgsbase bmi1 avx2 smep bmi2 rdseed adx smap clflushopt sha_ni xsaveopt xsavec xgetbv1 xsaves clzero irperf xsaveerptr arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif overflow_recov succor smca
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 8055.8 MB/s (0.5%)
C copy backwards (32 byte blocks) : 7984.9 MB/s (0.5%)
C copy backwards (64 byte blocks) : 7977.1 MB/s
C copy : 8073.6 MB/s
C copy prefetched (32 bytes step) : 8105.7 MB/s (0.3%)
C copy prefetched (64 bytes step) : 8076.9 MB/s (0.5%)
C 2-pass copy : 6989.1 MB/s (0.8%)
C 2-pass copy prefetched (32 bytes step) : 6998.8 MB/s (0.2%)
C 2-pass copy prefetched (64 bytes step) : 7071.2 MB/s (0.9%)
C fill : 10084.1 MB/s
C fill (shuffle within 16 byte blocks) : 10106.6 MB/s (0.4%)
C fill (shuffle within 32 byte blocks) : 10089.3 MB/s (0.3%)
C fill (shuffle within 64 byte blocks) : 10085.6 MB/s (0.2%)
---
standard memcpy : 14944.5 MB/s (0.6%)
standard memset : 12179.2 MB/s (0.8%)
---
MOVSB copy : 8316.3 MB/s
MOVSD copy : 8336.4 MB/s (0.6%)
SSE2 copy : 8958.2 MB/s (0.4%)
SSE2 nontemporal copy : 15260.3 MB/s (0.5%)
SSE2 copy prefetched (32 bytes step) : 8862.1 MB/s (0.6%)
SSE2 copy prefetched (64 bytes step) : 8838.1 MB/s (0.3%)
SSE2 nontemporal copy prefetched (32 bytes step) : 16071.8 MB/s (1.1%)
SSE2 nontemporal copy prefetched (64 bytes step) : 16075.9 MB/s (0.2%)
SSE2 2-pass copy : 7274.0 MB/s (0.6%)
SSE2 2-pass copy prefetched (32 bytes step) : 7815.5 MB/s (0.7%)
SSE2 2-pass copy prefetched (64 bytes step) : 7866.1 MB/s (0.3%)
SSE2 2-pass nontemporal copy : 4868.4 MB/s (0.6%)
SSE2 fill : 12187.2 MB/s (0.4%)
SSE2 nontemporal fill : 38292.0 MB/s (0.9%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 1.2 ns / 1.7 ns
131072 : 1.8 ns / 2.2 ns
262144 : 2.1 ns / 2.3 ns
524288 : 4.2 ns / 5.0 ns
1048576 : 7.6 ns / 9.6 ns
2097152 : 9.7 ns / 11.2 ns
4194304 : 11.2 ns / 12.0 ns
8388608 : 26.3 ns / 37.0 ns
16777216 : 56.5 ns / 74.9 ns
33554432 : 73.8 ns / 88.5 ns
67108864 : 83.7 ns / 94.3 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 1.2 ns / 1.7 ns
131072 : 1.8 ns / 2.2 ns
262144 : 2.1 ns / 2.3 ns
524288 : 2.4 ns / 2.5 ns
1048576 : 5.8 ns / 7.6 ns
2097152 : 7.6 ns / 9.1 ns
4194304 : 8.7 ns / 9.6 ns
8388608 : 16.7 ns / 23.1 ns
16777216 : 48.1 ns / 65.5 ns
33554432 : 63.8 ns / 77.5 ns
67108864 : 71.0 ns / 81.0 ns