AMD Phenom(tm) 8450 Triple Core Processor - ssvb/tinymembench GitHub Wiki
DDR2-800, dual channel memory (4GB)
BIOS settings:
Bank Interleving [Auto] Power Down Enable [Disabled]
/proc/cpuinfo
processor : 0 vendor_id : AuthenticAMD cpu family : 16 model : 2 model name : AMD Phenom(tm) 8450 Triple-Core Processor stepping : 3 microcode : 0x1000095 cpu MHz : 2100.000 cache size : 512 KB physical id : 0 siblings : 3 core id : 0 cpu cores : 3 apicid : 0 initial apicid : 0 fpu : yes fpu_exception : yes cpuid level : 5 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc rep_good nopl nonstop_tsc extd_apicid pni monitor cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs hw_pstate npt lbrv svm_lock bogomips : 4218.98 TLB size : 1024 4K pages clflush size : 64 cache_alignment : 64 address sizes : 48 bits physical, 48 bits virtual power management: ts ttp tm stc 100mhzsteps hwpstate processor : 1 vendor_id : AuthenticAMD cpu family : 16 model : 2 model name : AMD Phenom(tm) 8450 Triple-Core Processor stepping : 3 microcode : 0x1000095 cpu MHz : 2100.000 cache size : 512 KB physical id : 0 siblings : 3 core id : 1 cpu cores : 3 apicid : 1 initial apicid : 1 fpu : yes fpu_exception : yes cpuid level : 5 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc rep_good nopl nonstop_tsc extd_apicid pni monitor cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs hw_pstate npt lbrv svm_lock bogomips : 4218.98 TLB size : 1024 4K pages clflush size : 64 cache_alignment : 64 address sizes : 48 bits physical, 48 bits virtual power management: ts ttp tm stc 100mhzsteps hwpstate processor : 2 vendor_id : AuthenticAMD cpu family : 16 model : 2 model name : AMD Phenom(tm) 8450 Triple-Core Processor stepping : 3 microcode : 0x1000095 cpu MHz : 2100.000 cache size : 512 KB physical id : 0 siblings : 3 core id : 2 cpu cores : 3 apicid : 2 initial apicid : 2 fpu : yes fpu_exception : yes cpuid level : 5 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc rep_good nopl nonstop_tsc extd_apicid pni monitor cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs hw_pstate npt lbrv svm_lock bogomips : 4218.98 TLB size : 1024 4K pages clflush size : 64 cache_alignment : 64 address sizes : 48 bits physical, 48 bits virtual power management: ts ttp tm stc 100mhzsteps hwpstate
tinymembench v0.3.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 1993.6 MB/s
C copy : 2007.9 MB/s
C copy prefetched (32 bytes step) : 2037.3 MB/s
C copy prefetched (64 bytes step) : 2037.0 MB/s
C 2-pass copy : 1766.9 MB/s
C 2-pass copy prefetched (32 bytes step) : 1826.4 MB/s
C 2-pass copy prefetched (64 bytes step) : 1826.4 MB/s
C fill : 3242.9 MB/s
---
standard memcpy : 2010.4 MB/s
standard memset : 3261.6 MB/s
---
MOVSB copy : 2004.0 MB/s
MOVSD copy : 2003.9 MB/s
SSE2 copy : 2000.6 MB/s
SSE2 nontemporal copy : 3196.2 MB/s
SSE2 copy prefetched (32 bytes step) : 1998.1 MB/s
SSE2 copy prefetched (64 bytes step) : 1986.1 MB/s
SSE2 nontemporal copy prefetched (32 bytes step) : 3545.9 MB/s
SSE2 nontemporal copy prefetched (64 bytes step) : 3562.0 MB/s
SSE2 2-pass copy : 1743.6 MB/s
SSE2 2-pass copy prefetched (32 bytes step) : 1837.9 MB/s
SSE2 2-pass copy prefetched (64 bytes step) : 1857.5 MB/s
SSE2 2-pass nontemporal copy : 1050.6 MB/s
SSE2 fill : 3271.3 MB/s
SSE2 nontemporal fill : 4475.5 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 0.0 ns / 0.0 ns
131072 : 2.2 ns / 4.2 ns
262144 : 3.8 ns / 6.8 ns
524288 : 5.3 ns / 9.0 ns
1048576 : 13.0 ns / 20.0 ns
2097152 : 18.1 ns / 24.9 ns
4194304 : 50.3 ns / 72.3 ns
8388608 : 73.4 ns / 99.3 ns
16777216 : 85.5 ns / 111.7 ns
33554432 : 92.7 ns / 119.4 ns
67108864 : 100.1 ns / 130.7 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 0.0 ns / 0.0 ns
131072 : 2.2 ns / 4.2 ns
262144 : 3.3 ns / 6.0 ns
524288 : 3.8 ns / 6.8 ns
1048576 : 11.1 ns / 17.3 ns
2097152 : 15.8 ns / 21.8 ns
4194304 : 38.9 ns / 57.3 ns
8388608 : 57.8 ns / 77.1 ns
16777216 : 67.4 ns / 83.8 ns
33554432 : 72.2 ns / 86.2 ns
67108864 : 74.6 ns / 87.2 ns