Si510 and VersaClock 5 Phase Noise Measurements by KE5FX

John Miles, KE5FX, has kindly measured phase noise of the Si510 and VersaClock 5 for the Hermes-Lite project. You can find some of this other measurements here and here. Thank you, John!

61.440 MHz

Since I had spare 61.440 MHz SI510 parts, I put together a test board and setup config files for the VersaClock evaluation board for 61.440 MHz. Below are the results. The VersaClock evaluation board is using the onboard 25 MHz reference oscillator. There are two plots for the VersaClock 5. Plot 61440a in blue is the most precise divider, but may result in more spurs. Plot 61440b uses simpler fractional dividers for less spurs at the expense of frequency accuracy.

79.872 MHz

Below is a plot for 79.872 MHz, the target frequency for version 2.0. Again, plot a in blue is the most precise divider and plot b uses a simpler fractional divider. Noise is a bit higher as the output frequency is increased. These plots should be compared to similar plots in the VersaClock 5 datasheet and VersaClock 6 datasheet. These parts are pin compatible. Builders desiring the lowest phase noise can opt for the VersaClock 6.

79.872 MHz Assuming 10 MHz Reference

Although we did not measure with a 10 MHz reference, the plot below uses the same PLL settings to generate a 79.872 MHz clock with a 10 MHz reference. The actual output with the 25 MHz reference is nearly 200 MHz. I believe the increased phase noise at this frequency is primarily from the increased output frequency.

All Test Frequencies

Misc

John also provided a plot comparing against some other generators as well as comments below.

You can assume the spurs are real, at these levels. Most sources other than simple standalone oscillators will have a few spurs here and there, especially when fractional-N synthesizers are involved. The oscillator manufacturer has little incentive to reduce spurious content below what's needed by their customers. Once the relevant mask tests are passed, everybody goes home happy.

Beyond 1 kHz, these parts don't look too bad next to some higher-quality sources:

Most of the noise is probably due to the onboard crystal oscillator rather than the synthesizer chip itself. The spurs likely originate within the chip.

It's hard to say whether the IDT part is really that much better than the SiLabs part. If it were possible to drive the Si510 with a better external crystal oscillator, it might do just as well, or even better. As it stands, the inability to (easily) phase-lock the Si510 to an external source puts it at a disadvantage.

VersaClock 6 Phase Noise Measurements by W6EDY

I also asked IDT support for phase noise plots for the particular scenarios we are considering for Hermes-Lite V2. It was a pleasant surprise when Eddy van Keulen, W6EDY and IDT engineer, responded to my request. He provided the following plots for the VersaClock 6 with 25 MHz and 10 MHz references.

79.872 MHz with 25 MHz Reference

Below is the phase noise plot for generating 79.872 MHz with a 25 MHz reference. Eddy felt that this was a good result. It does agree with the IDT datasheet and follow a similar shape to what John Miles reported. The Agilent (Keysight) E5052 analyzers used by IDT are a standard in the frequency control industry. Note also that Eddy measured out to 10 MHz and revealed additional spurs. These are hopefully of low enough amplitude to not show up with the Hermes-Lite.

79.872 MHz with 10 MHz Reference

Below is the phase noise plot for generating 79.872 MHz with a 10 MHz reference. Eddy considered this a bad result given the -64.7 dBc spur at 10 MHz. He recommended the 25 MHz, or better yet a 26 MHz reference oscillator as they are commonly used in the cell phone industry. You can see that 79.872/26.0=3.072 is a simpler fraction than 79.872/25.0=3.19488.

This spur at 10 MHz with a 10 MHz reference means that it is not a good idea to drive the VersaClock directly with an external 10 MHz rubidium standard. A higher frequency standard must be used, or we can lock it to the 10 MHz reference via a digital controlled VCXO-style loop implemented in the FPGA.

This spur at 10 MHz also makes you wonder if there is always a bad spur at the reference clock frequency. To test this, I generated 79.872 MHz with my VersaClock 5 evaluation board, transmitted at 3.6 MHz, and looked for additional spurs at 28.6 MHz. Fortunately, I did not find any.

VersaClock 5 Versus Hermes-Lite PLL Frequency Doubling

These are a set of experiments to understand what differences one might notice between a Hermes-Lite using the onboard PLL or a VersaClock 5 to generate 76.8 MHz from a 38.4 MHz reference. They are not meant to be precise measurements of phase noise, but designed to show general trends in phase noise when integrated over wider frequencies and using typical SDR software for measurement.

Methodology

• Connect an alternate oscillator to the test Hermes-Lite receiver
• abr38.4
• cts38.4
• VersaClock 5 evaluation board set for simple frequency doubling with cts38.4 as reference oscillator.
• Si510 but at 73.728 MHz
• Connect a signal generator directly to Hermes-Lite receiver
  • The main signal generator was another standard Hermes-Lite running at 73.728 MHz. Both TX with and without interpolation were used. This Hermes-Lite generated a pure sinusoid at 28 MHz. A high frequency was picked to make the effects of phase noise more significant. The IAMP was used. A 33 Ohm resistor was placed across the TxDAC output as recommended by Claudio. A 100 Ohm resistor back terminated the AD9866 side of the transformer to reduce power. The transformer was the standard Hermes-Lite build. The v1.2 board reconstruction filter was used.
  • The alternate signal generator was the Rigol MSO2302A-S. This uses a 200 MHz 14-bit DAC to generate arbitrary waveforms including sine. The test frequency from this source was 21 MHz.
• Adjust signal source for maximum strength signal on receiver just before clipping
• This was done by both scaling down the spot value and TX power output in Quisk. Once scaled back, the same settings were used for the same Hermes-Lite test receiver.
• Take measurements every 5 kHz at 4800 Hz Digital USB bandwidth with hacked and automated Quisk across 10 MHz
• At each frequency step of 5 kHz, the script would pause for Quisk signal strength to stabilize, take 3 signal strength measurements 0.1 seconds apart, and then average. At each frequency, 0.5 seconds were required. About 15 minutes were required for a 10 MHz sweep. It is possible to speed this up, but the simplest changes to Quisk to get the job done were pursued.
• The Hermes-Lite receiver LNA was set to 0 dB gain.
• AGC was turned off.
• Repeat the above measurement but with signal generator off to provide a no-signal noise floor baseline
• Plot the results with matplotlib
• The readings were normalized so that the carrier was 0 dBFS. Without normalization, the carrier was typically -14.8 dB.

The biggest challenge, as seen below, was the phase noise already present in the signal generator.

Hermes-Lite TX Phase Noise

The plot below primarily illustrates the phase noise of the Hermes-Lite TX. The black line is with TX interpolation off. The blue line has TX interpolation on. The receiver used the cts38.4 oscillator doubled by the VersaClock 5 in both cases. First, notice the many low level spurs. These may come from the DAC, the ADC, the firmware DSP, or Quisk DSP. Even if the worst ones are truly in the TX signal, they are below 65 dBc. If you were to amplify this to a full kilowatt (60 dBm), these spurs would still only be -5 dBm or 0.3 mW. The trend line, or noise floor, is the important aspect to focus on.

If you follow the noise floor, it is interesting to see that with interpolation on, the TX has more close in phase noise but less far out. If you eyeball the total phase noise power (area under the curve), the TX with interpolation on appears to have less noise power. This surprised me as I thought the opposite would be true. With interpolation on, the PLL in the AD9866 creates a 2X73.728 MHz DAC clock. With interpolation off, the AD9866 could use the oscillator clock directly for the DAC clock, but it always generates the DAC clock via the VCO in the PLL, and hence the phase noise even for 1X. This may be considered a design flaw in the AD9866, but they are probably meeting the design requirements either way. Note again that at its peak, the phase noise is more than 80 dBc.

Fortunately, where it matters most, the external oscillator clock can be directly used for the ADC, so the phase noise of the AD9866's PLL can be bypassed during receive. This configuration is what we have been using with the Hermes-Lite. These experiments help us understand how using the AD9866's PLL for simple 2X impacts the receiver phase noise.

Finally, note that the baseline (no signal for receiver) plots are pretty much the same. This is reassuring that after normalization for dBFS the readings match up well. In all the data collected, there is a slight rise of 2 to 3 dB in this baseline as the frequency increases. I have never been able to explain this.

VersaClock 5 vs AD9866 PLL with Hermes-Lite Signal Source

The plot below uses the Hermes-Lite TX with interpolation on as the signal source. The red line is the cts38.4 oscillator doubled by the AD9866 PLL. The blue line is the same cts38.4 oscillator doubled by a VersaClock 5. Besides the switch in oscillator, all other variables (Hermes-Lite board, power supply, settings, etc.) are the same for both readings.

You can clearly see that the Hermes-Lite using the AD9866 PLL is seeing more phase noise. The worse spur is for the AD9866 PLL and is only 55 dBc.

The baseline readings are stil almost identical. As before, there is a spur at 26.8 MHz even with no TX signal present. This may be an issue with the firmware DSP for the new 76.8 MHz clock frequency and requires more investigation.

VersaClock 5 vs AD9866 PLL with Rigol Signal Source

The plot below uses the Rigol signal source at 21 MHz. Again, the red line is the cts38.4 oscillator doubled by the AD9866 PLL and the blue line is the same cts38.4 oscillator doubled by a VersaClock 5. There are more spurs with this signal source, and the phase noise distribution is different. Still, the same trend of worse phase noise with the AD9866 PLL is seen.

All

The plot below adds a Hermes-Lite using the abr38.4 oscillator and another using the standard Si510 73.728 MHz to the mix. For these measurements, the signal source is a Hermes-Lite TX but with interpolation off. With interpolation off, it is harder to see the additive rises in phase noise for the AD9866 PLL over the TX phase noise. Still, close in one can see the two oscillators used with the AD9866 PLL rise. It is interesting to note that the abr38.4 oscillator appears better than the cts38.4. The abr38.4 oscillator was actually on a different Hermes-Lite, so differences in the AD9866 may be a factor here.

It is also interesting to note that the Si510 at 73.728 MHz does not have the RX spur at 26.8 MHz. Also, the baseline far out noise appears better. This was also with a different Hermes-Lite, so differences in the multiple AD9866s may again be a factor.

WSPR Spot Tests

I also ran 2 days of head-to-head WSPR spots between a Hermes-Lite with the abr38.4 ocsillator doubled by the AD9866 and another Hermes-Lite with the cts38.4 oscillator doubled by the VersaClock 5. Both units were connected to the same antenna by a simple tee. Two copies of Quisk and two copies of WSPRX, all with the same settings, were run on the same NTP time-calibrated computer. Over two days, I collected spots on 20 and 40 meters. After the first day, I swapped frontend cards between the units. The frequencies of both units were adjusted so that WSPR spots differed by at most 1 Hz. It was nice to see that the abr38.4 oscillator at 500 ppb was pretty much right on the money.

As seen below, the results for both units pretty much agreed. I am surprised there weren't more differences. If one unit would have to get the edge, it would be the one with the abr38.4 oscillator using the AD9866 PLL. But there results are so close that it could just be differences in the two AD9866s. Swapping the frontends made no difference.

Unit	abr38.4 with AD9866 PLL	cts38.4 with VersaClock 5
Total Spots	1641	1638
Unique Spots	31	28
Spots with dB Advantage	131	128
Average dB Advantage	1.02	1.09