SCN - sjsoftware/centurion-cpu6 GitHub Wiki
SCN - (Scan) Find the first occurrence of a character type in a string
| Selector | Opcode | 1st Operand | 2nd Operand | 3rd Operand |
|---|---|---|---|---|
| 3 | SCN | Length - 1 | Memory | Memory |
Operand 1 is length byte Operand 2 is memory address (table) Operand 3 is memory address (string)
On entry B holds two bytes - low byte is used with string, high byte is used with table.
BL is ANDed with first byte of string. (e.g., mask out high bit on string) BH is ANDed with the byte at the destination address plus the result. If this is zero, and there's still bytes left, repeat by ANDing BL with the next byte of source. (e.g., mask for character type) If there's no bytes left set fault. If the AND of BH and destination is non-zero set BL to the result of the destination AND and AL to the remaining length. Y and Z (might be Z and Y) are set to the table entry address and address in string
This is finding the first occurrence of a character type in a string.
Microcode
03a 0 CRY0 r00 r09 RAM NOT.D P P P 002 02 (fd) LOAD.RIR READ.CONST (03a) r09 <- 2; RIR <- r09 ;* B
03b 1 RLO CRY0 r00 r00 PASS A+Q D D D 4e0 e0 (1f) LOAD.MAR READ.SWP (03b) MAR <- WAR ;* dest
1 CRY0 r00 r01 RAM D P P P 004 04 (fb) BUS.RD LOAD.CCR READ.RF (4e0) r01 <- RF (low); CCR ;* set fault
0 CRY0 r00 r04 RAM D P P P 643 43 (bc) JSR BADR READ.RF (4e1) r04 <- RF (high)
0 CRY0 r00 r00 PASS A+Q P P P 785 85 (7a) JSR DMA BUS.WAIT READ.SWP (4e2)
0 CRY0 r01 r00 RAM D.AND.A P P P 73e 3e (c1) JSR PE READ.DB (4e3) r00 <- DB & r01
0 CRY0 r00 r07 PASS A+B D D D 750 50 (af) LOAD.FLR LOAD.RR READ.SWP (4e4)
0 CRY r05 r00 PASS A+0 D D D 760 60 (9f) LOAD.ALO LOAD.RR READ.SWP (750)
0 CRY0 r00 r00 PASS A+Q D D D 752 52 (ad) LOAD.AHI READ.SWP (760)
0 CRY0 r00 r00 PASS A+Q D D D 756 56 (a9) LOAD.AHI LOAD.ALO LOAD.MAR READ.SWP (752) ;* reload src (and swap into MAR)
0 CRY0 r00 r00 PASS A+Q D D D 761 61 (9e) BUS.RD READ.SWP (756)
0 CRY0 r00 r00 PASS A+Q P P P 643 43 (bc) JSR BADR READ.SWP (761)
0 CRY0 r00 r00 PASS A+Q P P P 785 85 (7a) JSR DMA BUS.WAIT READ.SWP (762)
0 CRY0 r04 r02 RAM D.AND.A P P P 73e 3e (c1) JSR PE LOAD.FLR READ.DB (763) r02 <- DB & r04
0 CRY0 r03 r00 PASS A COND Z P P D PUSH 0c5 c5 (3a) LOAD.FLR READ.SWP (764) r03; BSR (zero) 767
0 CRY0 r02 r00 PASS A D D D 7c4 c4 (3b) LOAD.RR READ.SWP (765)
1 RLO CRY0 r00 r00 PASS ZERO D D D 7c6 c6 (39) WRITE.RF LOAD.RIR READ.SWP (7c4) ;* BL <- r02
0 CRY0 r03 r00 PASS A D D D 7c8 c8 (37) LOAD.RR READ.SWP (7c6)
1 RLO CRY0 r00 r00 PASS D D D D 1d1 d1 (2e) WRITE.RF LOAD.RR READ.ALO (7c8) BRT 1d1 ;* common tail to write Y and Z and exit
767 0 CRY0 r00 r00 PASS A+Q COND Z P P D 0c9 c9 (36) READ.SWP (767) BRT (zero) 76b
0 CRY0 r03 r03 RAM A-1 D D D POP 03b 3b (c4) INC.WAR READ.SWP (769) r03--; POP; BRT 03b
76b 0 CRY0 r00 r00 PASS A+Q S S S POP 008 08 (f7) LOAD.CCR READ.SWP (76b) ;* overrun set fault and return