CVX - sjsoftware/centurion-cpu6 GitHub Wiki
CVX - Convert Executable
Pseudocode
pseudocode for this:
CVX(base, src)
chk = 0
type = *src++
chk += type
length = *src++
chk += length
chk += *src
addr(high) = *src++
chk += src
addr(low) = *src++
dest = base + addr
A = dest
if (type == 80) {
set flags V, L, keep F
Z = src
return
}
if (type == 0) {
if (length == 0) {
set flags V, keep L, F
}
while (length-- > 0) {
chk += *src
*dest++ = *src++
}
chk += *src++
set F if chk <> 0
Z = src
return
}
if (type == 1 || type == -1) {
if (length & 1 == 1) {
set flags F, keep L
return
}
while (length > 0) {
chk += *src;
addr(high) = *src++
chk += *src
addr(low) = *src++
dest = base + addr
fixup(high) = *dest(high)
fixup(low) = *dest(low)
op = type
do {
if (op == 0) {
*dest(high) = fixup(high)
*dest(low) = fixup(high)
length -= 2;
break;
}
if (op == 1) {
fixup = fixup + A
op--
}
if (op == -1) {
fixup = fixup - A
op++
}
} while (length > 0)
}
chk += *src++
set F from chk
Z = src
}
Microcode
;* 47 0x
;* A returned with starting address
;* Z returned with ending address (next address to write)
;* MAR - op 1 - destination address base
;* WAR - op 2 - buffer with record
00a 0 CRY0 r00 r00 PASS A+Q P P D 102 02 (fd) BUS.RD LOAD.CCR READ.SWP (00a) ;* Flags => 0
0 CRY0 r00 r00 PASS A+Q P P P 643 43 (bc) JSR BADR READ.SWP (002)
0 CRY0 r00 r02 RAM NOT.D D D D 680 80 (7f) BUS.WAIT INC.MAR READ.CONST (003) r02 <- 80
0 CRY0 r00 r00 RAM D P P P 1be be (41) JSR PE BUS.RD READ.DB (680) r00 <- DB
0 CRY0 r00 r00 PASS A+Q P P P 643 43 (bc) JSR BADR READ.SWP (681)
0 CRY0 r00 r00 PASS A+Q P P P 785 85 (7a) JSR DMA BUS.WAIT LOAD.AHI LOAD.ALO LOAD.MAR READ.SWP (682) ;* swap ARs
0 CRY0 r00 r01 RAM D P P P 70e 0e (f1) JSR PE BUS.RD READ.DB (683) r01 <- DB ;* this is destination base
0 CRY0 r00 r00 PASS A+Q P P P 643 43 (bc) JSR BADR READ.SWP (684)
0 CRY0 r00 r00 PASS A+Q D D D 587 87 (78) BUS.WAIT INC.MAR READ.SWP (685)
0 CRY0 r02 r00 PASS D.XOR.A P P P 74e 4e (b1) JSR PE LOAD.FLR READ.DB (587) r02 ^ DB
0 CRY0 r00 r02 RAM D COND Z P P D 0c9 c9 (36) READ.DB (588) r02 <- DB; BRT (zero) 58b ;* type
;* type not 0x80
0 CRY0 r02 r07 RAM A D D D 0d0 d0 (2f) BUS.RD READ.SWP (589) r07 <- r02 ;* r07 is checksum
0 CRY0 r00 r00 PASS A+Q P P P 643 43 (bc) JSR BADR READ.SWP (0d0)
0 CRY0 r00 r00 PASS A+Q D D D 031 31 (ce) BUS.WAIT INC.MAR READ.SWP (0d1)
0 CRY0 r00 r03 RAM D P P P 1be be (41) JSR PE BUS.RD READ.DB (031) r03 <- DB ;* length
0 CRY0 r03 r07 RAM A+B P P P 643 43 (bc) JSR BADR READ.SWP (032) r07 += r03
0 CRY0 r00 r00 PASS A+Q D D D 0bd bd (42) BUS.WAIT INC.MAR READ.SWP (033)
0 CRY0 r00 r04 RAM D P P P 1be be (41) JSR PE BUS.RD READ.DB (0bd) r04 <- DB ;* addr (high)
0 CRY0 r04 r07 RAM A+B P P P 643 43 (bc) JSR BADR READ.SWP (0be) r07 += r04
0 CRY0 r00 r09 RAM ZERO D D D 050 50 (af) BUS.WAIT INC.MAR LOAD.RIR READ.SWP (0bf) r09 <- 0; RIR <- r09 ;* A - receives destination address
0 CRY0 r07 r07 RAM D+A P P P 74e 4e (b1) JSR PE READ.DB (050) r07 += DB
0 CRY0 r01 r05 RAM D+A D D D 022 22 (dd) LOAD.FLR LOAD.RR READ.DB (051) r05 = r01 + DB; RR <- r05 ;* addr (low) - base + address
1 RLO CRY r00 r04 RAM A+B D D D 553 53 (ac) WRITE.RF READ.SWP (022) r04 += r00 + c; RF <- RR ;* r04/r05 has destination address, load it into WAR
0 CRY0 r04 r00 PASS A P P P 785 85 (7a) JSR DMA LOAD.ALO LOAD.RR READ.SWP (553) ALO <- RR ;* WAR ==> destination
1 CRY0 r02 r00 PASS A D D D 5ae ae (51) LOAD.FLR WRITE.RF READ.SWP (554) r02; RF <- RR ;* check type
0 CRY0 r03 r00 PASS A COND Z P P D 0c1 c1 (3e) LOAD.FLR LOAD.AHI READ.SWP (5ae) r03; AHI <- RR BRT (zero) 5a3
;* type not zero (type == 1 or -1, possibly others are possible as well?)
0 CRY0 r03 r00 PASS D.AND.A P P P 0fe fe (01) LOAD.FLR READ.CONST (5a1) r03 & 1 ;* r03 odd?
0 CRY0 r00 r00 PASS A+Q COND Z P P D 0cd cd (32) READ.SWP (5a2) BRT (zero) 5af
;* r03 odd (length odd) - fault!
0 CRY0 r00 r09 RAM D D D D 0a1 a1 (5e) LOAD.RIR READ.CONST (5ad) r09 <- 5e; RIR <- r09
1 RLO CRY0 r00 r00 PASS A+Q P P P 009 09 (f6) LOAD.CCR READ.SWP (0a1) CCR ;* set fault, minus and zero set from r03 test, keep link
1 CRY0 r00 r00 PASS D D D D 4b4 b4 (4b) LOAD.RR READ.RF (0a2) ;* set PC from P
0 CRY0 r00 r00 PASS D P P P 785 85 (7a) JSR DMA LOAD.ALO LOAD.RR READ.RF (4b4) ;* common tail from somewhere
0 CRY0 r00 r00 PASS A+Q D D D 3e6 e6 (19) LOAD.AHI READ.SWP (4b5)
0 CRY0 r00 r00 PASS A+Q D D D 100 00 (ff) LOAD.MAR READ.SWP (3e6) ;* exit
;* r03 even - do relocations
5af 0 CRY0 r00 r00 PASS A+Q D D D 5b4 b4 (4b) BUS.RD READ.SWP (5af)
5b4 0 CRY0 r00 r00 PASS A+Q P P P 643 43 (bc) JSR BADR READ.SWP (5b4)
0 CRY0 r00 r00 PASS A+Q D D D 532 32 (cd) BUS.WAIT INC.MAR READ.SWP (5b5)
0 CRY0 r00 r04 RAM D P P P 1be be (41) JSR PE BUS.RD READ.DB (532) r04 <- DB
0 CRY0 r07 r07 RAM D+A P P P 643 43 (bc) JSR BADR READ.DB (533) r07 += DB
0 CRY0 r00 r00 PASS A+Q D D D 5b0 b0 (4f) BUS.WAIT INC.MAR READ.SWP (534)
0 CRY0 r01 r00 PASS D+A P P P 74e 4e (b1) JSR PE LOAD.FLR LOAD.RR READ.DB (5b0) RR <- r01 + DB
0 CRY0 r07 r07 RAM D+A D D D 574 74 (8b) LOAD.ALO READ.DB (5b1) ALO <- RR; r07 += DB
0 CRY r04 r00 PASS A+B P P P 785 85 (7a) JSR DMA LOAD.RR READ.SWP (574) r00 += r04 + c; RR <- r00
0 CRY0 r00 r00 PASS A+Q D D D 540 40 (bf) LOAD.AHI READ.SWP (575) AHI <- RR
0 CRY0 r00 r00 PASS A+Q D D D 570 70 (8f) LOAD.AHI LOAD.ALO LOAD.MAR READ.SWP (540) swap ARs
0 CRY0 r00 r00 PASS A+Q D D D 5f4 f4 (0b) BUS.RD READ.SWP (570)
0 CRY0 r00 r00 PASS A+Q P P P 643 43 (bc) JSR BADR READ.SWP (5f4)
0 CRY0 r00 r00 PASS A+Q D D D 542 42 (bd) BUS.WAIT INC.MAR READ.SWP (5f5)
0 CRY0 r00 r04 RAM D P P P 1be be (41) JSR PE BUS.RD READ.DB (542) r04 <- DB
0 CRY0 r00 r06 PASS A+Q P P P 643 43 (bc) JSR BADR DIR- READ.SWP (543)
0 CRY0 r02 r08 RAM A D D D 5a4 a4 (5b) BUS.WAIT INC.MAR READ.SWP (544) r08 <- r02 ;* start off at type (1) - go back so we can write
0 CRY0 r02 r07 PASS A P P P 72e 2e (d1) JSR PE LOAD.FLR DIR+ READ.SWP (5a4) r02
1 RLO CRY0 r00 r05 RAM D COND ???? D D D 5c0 c0 (3f) READ.DB (5a5) r05 <- DB; switch (r02 - zero/minus) ;* r04/r05 = value at r01/r02 + address
;* non-zero, plus (type = 1, add base)
5c0 1 CRY0 r05 r05 RAM D+A D D D 04e 4e (b1) LOAD.FLR READ.RF (5c0) r05 += RF (low)
0 CRY r04 r04 RAM D+A P P P 785 85 (7a) JSR DMA READ.RF (04e) r04 += RF (hign) + c
0 CRY0 r00 r08 RAM B-1 D D D 05e 5e (a1) LOAD.FLR READ.SWP (04f) r08--
05e 1 RLO CRY0 r00 r00 PASS A+Q COND ???? D D D 5c0 c0 (3f) READ.SWP (05e) switch (r08 - zero/minus)
;* non-zero, minus (type = -1, subtract base)
5c1 1 CRY1 r05 r05 RAM A-D-1 D D D 05c 5c (a3) LOAD.FLR READ.RF (5c1) r05 -= RF (low) ;* non-zero, minus
0 CRY r04 r04 RAM A-D-1 P P P 785 85 (7a) JSR DMA READ.RF (05c) r04 -= RF + c (high)
0 CRY1 r00 r08 RAM B+0 P P P 000 00 (ff) LOAD.FLR READ.SWP (05d) r08++; BRT 05e
;* zero, plus (store result)
5c2 0 CRY0 r04 r00 PASS A D D D 0cd cd (32) LOAD.DBR LOAD.RR READ.SWP (5c2) DBR <- r04
0 CRY0 r00 r00 PASS A+Q D D D 03c 3c (c3) BUS.WT READ.SWP (0cd)
0 CRY0 r00 r00 PASS A+Q P P P 5cc cc (33) JSR BADW READ.SWP (03c)
0 CRY0 r00 r00 PASS A+Q P P P 785 85 (7a) JSR DMA BUS.WAIT INC.MAR READ.SWP (03d)
0 CRY0 r05 r05 RAMA NOT.D P P P 080 80 (7f) LOAD.DBR LOAD.RR READ.CONST (03e) DBR <- r05; r05 <- 80
0 CRY0 r05 r03 RAMA B-1 D D D 08e 8e (71) BUS.WT LOAD.SAR READ.SWP (03f) SAR <- r05; r03--
0 CRY0 r00 r03 RAM B-1 P P P 5cc cc (33) JSR BADW LOAD.FLR READ.SWP (08e) r03--
0 CRY0 r00 r00 PASS A+Q COND Z D A D 0c9 c9 (36) BUS.WAIT LOAD.MAR READ.SWP (08f) dispatch (r03 not zero, 089, r03 zero 08b) ;* are we done?
089 0 CRY0 r00 r00 PASS A+Q D D D 5b4 b4 (4b) BUS.RD READ.SWP (089) BRT 5b4 ;* not done
;* r02 zero (type == 0)
5a3 0 CRY0 r00 r00 PASS A+Q COND Z P P D 0c9 c9 (36) READ.SWP (5a3) BRT (!zero) 5a9 ;* check r03
5ab 0 CRY0 r00 r00 PASS A+Q P P P 011 11 (ee) LOAD.CCR READ.SWP (5ab) CCR ; set value, minus, keep link and fault (will set to zero)
0 CRY0 r00 r00 PASS A+Q D D D 08b 8b (74) READ.SWP (5ac) BRT 08b
;* r03 not zero read bytes from src and write to dest
5a9 0 CRY0 r00 r00 PASS A+Q D D D 10b 0b (f4) BUS.RD READ.SWP (5a9)
0 CRY0 r00 r00 PASS A+Q P P P 643 43 (bc) JSR BADR READ.SWP (10b)
0 CRY0 r00 r00 PASS A+Q P P P 785 85 (7a) JSR DMA BUS.WAIT INC.MAR READ.SWP (10c)
0 CRY0 r07 r07 RAM D+A P P P 76e 6e (91) JSR PE LOAD.AHI LOAD.ALO LOAD.MAR READ.DB (10d)
0 CRY0 r00 r00 PASS D D D D 55c 5c (a3) LOAD.DBR LOAD.RR READ.DB (10e)
0 CRY0 r00 r00 PASS A+Q D D D 592 92 (6d) BUS.WT READ.SWP (55c)
0 CRY0 r00 r03 RAM B-1 P P P 5cc cc (33) JSR BADW LOAD.FLR READ.SWP (592) r03--
0 CRY0 r00 r00 PASS A+Q COND Z P P D 0c5 c5 (3a) BUS.WAIT LOAD.AHI LOAD.ALO LOAD.MAR READ.SWP (593) BRT (zero) 597
0 CRY0 r00 r00 PASS A+Q D D D 5a9 a9 (56) INC.WAR READ.SWP (595) BRT 5a9
597 0 CRY0 r00 r00 PASS A+Q D D D 08b 8b (74) READ.SWP (597) BRT 08b
;* r03 zero - end of loop
08b 0 CRY0 r00 r09 RAM NOT.D P P P 00e 0e (f1) BUS.RD LOAD.RIR READ.CONST (08b) r09 <- e ;* P
0 CRY0 r00 r00 PASS A+Q P P P 643 43 (bc) JSR BADR READ.SWP (08c)
0 CRY0 r00 r00 PASS A+Q D D D 0a4 a4 (5b) BUS.WAIT INC.MAR READ.SWP (08d)
0 CRY0 r07 r07 RAM D+A P P P 74e 4e (b1) JSR PE LOAD.FLR READ.DB (0a4) r07 += DB ;* checksum
1 RLO CRY0 r00 r00 PASS ZERO COND Z P P D 0c1 c1 (3e) LOAD.FLR READ.SWP (0a5) r00; BRT !zero 0a1 ;* fault!
0a3 0 CRY0 r00 r00 PASS A+Q D D D 086 86 (79) READ.SWP (0a3) BRT 086 ;* write out Z and finish up
;* type 0x80
58b 0 CRY0 r00 r00 PASS A+Q P P P 0d1 d1 (2e) LOAD.CCR READ.SWP (58b) CCR ;* set CCR (minus clear, zero set, keep F, link set)
0 CRY0 r00 r00 PASS A+Q D D D 086 86 (79) READ.SWP (58c)
086 0 CRY0 r00 r00 RAM NOT.D P P P 0f0 f0 (0f) READ.CONST (086) r00 <- f0
0 CRY0 r00 r00 PASS NOT.D P P P 008 08 (f7) LOAD.RIR READ.CONST (087) RIR <- 8 ;* write address into Z - this should be one past the src record, it's the address of the start of the next record
0 CRY0 r00 r00 PASS D D D D 06c 6c (93) LOAD.RR READ.ALO (088) RR <- ALO
1 RLO CRY0 r00 r00 PASS D.XOR.A D D D 07c 7c (83) WRITE.RF LOAD.RR READ.AHI (06c)
1 CRY0 r00 r00 PASS A+Q D D D 5e4 e4 (1b) WRITE.RF READ.SWP (07c) BRT 5e4 ;* common tail