20160726_jeffrey - silenceuncrio/diary GitHub Wiki

Index

0910 - AVNET CPU 公板 emmc 開機
0920 - Frank 回信
1015 - 致電 mike
1030 - imximage.cfg u-boot.bin u-boot.imx
1310 - <UBOOT_SRC> 另存 <UBOOT_SRC_NAND>
1405 - u-boot.imx SD Card - <UBOOT_SRC> 或 <UBOOT_SRC_NAND> 可以從 SD Card 開機
1820 - 研究 GPIO 點燈
1915 - 觀察 <UBOOT_SRC>/board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg DCD

0910

昨晚又收到不少關注

早上 morris 拿了一片 AVNET 的 CPU 公板給我

這一塊使用的就是 emmc, 一開機就跑起來了

不過 morris 說那一塊 emmc 是 micron 的除了比較貴之外, 交期也有點長

我們繼續試 NAND Flash

0920

Frank 回信了

不過情報量落後我們許多

Dear Frank,
thanks for your response
.

Do you compare uboot code and NAND DUMP code ? Are they same ?
yes, they are same
I just want to confirm below H/W jumper setting whether correct at NAND boot ?
a. D1=ON, D2=OFF of SW602
b. D1=ON, D2=ON, D3=OFF, D4=ON of SW601
c. Remove the QSPI Nor Flash
yes
but D3 need be OFF
actually we try all possible combination of SW601
.
BR
Jeffrey

1015

致電 mike 聊了一下

才發現他都不看 mail 的

沒差... 電話聊一下也可以啦

1030

目前在尋找下述三者的關聯

<UBOOT_SRC>/board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg <UBOOT_SRC>/u-boot.bin <UBOOT_SRC>/u-boot.imx

直接在 <UBOOT_SRC> 使用下述的 command 來 build image

make distclean
make mx6ul_14x14_evk_nand_defconfig
make

過程紀錄在 2016-07-26-u-boot-make.log

注意最後的過程

  ...
  LDS     u-boot.lds
  LD      u-boot
  OBJCOPY u-boot.bin
  CFGS    board/freescale/mx6ul_14x14_evk/imximage.cfg.cfgtmp
  MKIMAGE u-boot.imx
  OBJCOPY u-boot.srec

先產生出 u-boot.bin

經由 CFGS board/freescale/mx6ul_14x14_evk/imximage.cfg.cfgtmp

再產生出 u-boot.imx

Box:~/M300/fsl-release-bsp/build_small/tmp/work/imx6ulevk-poky-linux-gnueabi/u-boot-imx/2015.04-r0/git$ ls -al u-boot.bin u-boot.imx
-rwxrwxr-x 1 jeffrey jeffrey 406988  7月 25 18:43 u-boot.bin
-rw-rw-r-- 1 jeffrey jeffrey 412672  7月 25 18:43 u-boot.imx

可以發現 u-boot.imx 多了 u-boot.bin 412672 - 406988 = 5684 bytes

從檔案的開頭開始看的話可以發現 u-boot.imx 多了 u-boot.bin 這些東西

d100 2040 0000 8087 0000 0000 2cf4 7f87
20f4 7f87 00f4 7f87 0000 0000 0000 0000
00f0 7f87 0050 0600 0000 0000 d201 e040
cc01 dc04 020c 4068 ffff ffff 020c 406c
ffff ffff 020c 4070 ffff ffff 020c 4074
ffff ffff 020c 4078 ffff ffff 020c 407c
ffff ffff 020c 4080 ffff ffff 020e 04b4
000c 0000 020e 04ac 0000 0000 020e 027c
0000 0030 020e 0250 0000 0030 020e 024c
0000 0030 020e 0490 0000 0030 020e 0288
0000 0030 020e 0270 0000 0000 020e 0260
0000 0030 020e 0264 0000 0030 020e 04a0
0000 0030 020e 0494 0002 0000 020e 0280
0000 0030 020e 0284 0000 0030 020e 04b0
0002 0000 020e 0498 0000 0030 020e 04a4
0000 0030 020e 0244 0000 0030 020e 0248
0000 0030 021b 001c 0000 8000 021b 0800
a139 0003 021b 080c 0000 0000 021b 083c
4149 0145 021b 0848 4040 4546 021b 0850
4040 524d 021b 081c 3333 3333 021b 0820
3333 3333 021b 082c f333 3333 021b 0830
f333 3333 021b 08c0 0092 1012 021b 08b8
0000 0800 021b 0004 0002 002d 021b 0008
0033 3030 021b 000c 676b 52f3 021b 0010
b66d 8b63 021b 0014 01ff 00db 021b 0018
0020 1740 021b 001c 0000 8000 021b 002c
0000 26d2 021b 0030 006b 1023 021b 0040
0000 004f 021b 0000 8418 0000 021b 001c
0200 8032 021b 001c 0000 8033 021b 001c
0004 8031 021b 001c 1520 8030 021b 001c
0400 8040 021b 0020 0000 0800 021b 0818
0000 0227 021b 0004 0002 552d 021b 0404
0001 1006 021b 001c 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
...
0000 0000 0000 0000 0000 0000 0000 0000

觀察 <UBOOT_SRC>/board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg

/*
 * Copyright (C) 2015 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Refer docs/README.imxmage for more details about how-to configure
 * and create imximage boot image
 *
 * The syntax is taken as close as possible with the kwbimage
 */

#define __ASSEMBLY__
#include <config.h>

/* image version */

IMAGE_VERSION 2

/*
 * Boot Device : one of
 * spi/sd/nand/onenand, qspi/nor
 */

#ifdef CONFIG_SYS_BOOT_QSPI
BOOT_FROM	qspi
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
BOOT_FROM	nor
#else
BOOT_FROM	sd
#endif

#ifdef CONFIG_USE_PLUGIN
/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
PLUGIN	board/freescale/mx6ul_14x14_ddr3_arm2/plugin.bin 0x00907000
#else

#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif

/*
 * Device Configuration Data (DCD)
 *
 * Each entry must have the format:
 * Addr-type           Address        Value
 *
 * where:
 *	Addr-type register length (1,2 or 4 bytes)
 *	Address	  absolute address of the register
 *	value	  value to be stored in the register
 */

DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
DATA 4 0x020c4084 0xffffffff

DATA 4 0x020E04B4 0x000C0000
DATA 4 0x020E04AC 0x00000000
DATA 4 0x020E027C 0x00000030
DATA 4 0x020E0250 0x00000030
DATA 4 0x020E024C 0x00000030
DATA 4 0x020E0490 0x00000030
DATA 4 0x020E0288 0x00000030
DATA 4 0x020E0270 0x00000000
DATA 4 0x020E0260 0x00000030
DATA 4 0x020E0264 0x00000030
DATA 4 0x020E04A0 0x00000030
DATA 4 0x020E0494 0x00020000
DATA 4 0x020E0280 0x00000030
DATA 4 0x020E0284 0x00000030
DATA 4 0x020E04B0 0x00020000
DATA 4 0x020E0498 0x00000030
DATA 4 0x020E04A4 0x00000030
DATA 4 0x020E0244 0x00000030
DATA 4 0x020E0248 0x00000030

DATA 4 0x021B001C 0x00008000
DATA 4 0x021B0800 0xA1390003
DATA 4 0x021B080C 0x0013000F
DATA 4 0x021B083C 0x415D0159
DATA 4 0x021B0848 0x4040484F
DATA 4 0x021B0850 0x40405247
DATA 4 0x021B081C 0x33333333
DATA 4 0x021B0820 0x33333333
DATA 4 0x021B082C 0xf3333333
DATA 4 0x021B0830 0xf3333333
DATA 4 0x021B08C0 0x00922012
DATA 4 0x021B08b8 0x00000800
DATA 4 0x021B0004 0x0002002D
DATA 4 0x021B0008 0x1B333000
DATA 4 0x021B000C 0x676B54B3
DATA 4 0x021B0010 0xB68E0A83
DATA 4 0x021B0014 0x01FF00DB
DATA 4 0x021B0018 0x00211740
DATA 4 0x021B001C 0x00008000
DATA 4 0x021B002C 0x000026D2
DATA 4 0x021B0030 0x006B1023
DATA 4 0x021B0040 0x0000005F
DATA 4 0x021B0000 0x85180000
DATA 4 0x021B001C 0x02008032
DATA 4 0x021B001C 0x00008033
DATA 4 0x021B001C 0x00048031
DATA 4 0x021B001C 0x15208030
DATA 4 0x021B001C 0x04008040
DATA 4 0x021B0020 0x00000800
DATA 4 0x021B0818 0x00000227
DATA 4 0x021B0004 0x0002552D
DATA 4 0x021B0404 0x00011006
DATA 4 0x021B001C 0x00000000
#endif

Device Configuration Data (DCD) 的相關部分正好出現在 u-boot.imx 多出來的部分

imximage.cfg 提到

 * Refer docs/README.imxmage for more details about how-to configure
 * and create imximage boot image

就來看看 README.imxmage

複製到 gist - README.imxmage

1310

將目前的 <UBOOT_SRC> 另存一份 /home/jeffrey/M300/fsl-release-bsp/build_small/tmp/work/imx6ulevk-poky-linux-gnueabi/u-boot-imx-nand

已確認下述的 command build image 是成功的

make distclean
make mx6ul_14x14_evk_nand_defconfig
make

稱為 <UBOOT_SRC_NAND>

在 <POKY_DIR> 使用

bitbake u-boot-imx -c clean
bitbake u-boot-imx -c unpack

重新得到乾淨的 <UBOOT_SRC>

source /opt/poky/2.1/environment-setup-armv7a-neon-poky-linux-gnueabi
make distclean
make mx6ul_14x14_evk_defconfig
make

得到 u-boot.imx

利用 MfgTool 寫到 NAND Flash

從 NAND Flash 開機... 失敗

1405

參考 i.MX Linux® User's Guide

4.3.3 Partitioning the SD/MMC card
4.3.4 Copying a bootloader image

將 u-boot.imx copy 到 SD Card 去

不管是使用 <UBOOT_SRC> 或是 <UBOOT_SRC_NAND> 都可以順利地從 SD Card 開機

研究一下 <UBOOT_SRC>/board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg

關於 Device Configuration Data (DCD) 的部分

i.MX 6UltraLite Applications Processor Reference Manual
- Chapter 8 System Boot
  - 8.7 Program image
    - 8.7.2 Device Configuration Data (DCD)

1820

研究怎麼利用 GPIO 來點燈

i.MX 6UltraLite Applications Processor Reference Manual
- Chapter 26 General Purpose Input/Output (GPIO)
  - 26.4 GPIO Functional Description
    - 26.4.3 GPIO Programming
      - 26.4.3.2 GPIO Write Mode

再配合 <UBOOT_SRC>/board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg 去改 DCD 觀察點燈的動作是否被執行

26.4.3.2 GPIO Write Mode

The programming sequence for driving output signals should be as follows:

Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need to read loopback pad value through PSR
Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b).
Write value to data register (GPIO_DR).

A pseudocode description to drive 4'b0101 on [output3:output0] is as follows:

// SET PADS TO GPIO MODE VIA IOMUX. 
write sw_mux_ctl_pad_<output[0-3]>.mux_mode, <GPIO_MUX_MODE>
// Enable loopback so we can capture pad value into PSR in output mode 
write sw_mux_ctl_pad_<output[0-3]>.sion, 1
// SET GDIR=1 TO OUTPUT BITS. 
write GDIR[31:4,output3_bit,output2_bit, output1_bit, output0_bit,] 32'hxxxxxxxF
// WRITE OUTPUT VALUE=4’b0101 TO DR. 
write DR, 32'hxxxxxxx5
// READ OUTPUT VALUE FROM PSR ONLY. 
read_cmp PSR, 32'hxxxxxxx5

1915

先觀察 <UBOOT_SRC>/board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg 的 DCD 都在做啥

DATA 4 0x020c4068 0xffffffff CCM Clock Gating Register 0 (CCM_CCGR0)
DATA 4 0x020c406c 0xffffffff CCM Clock Gating Register 1 (CCM_CCGR1)
DATA 4 0x020c4070 0xffffffff CCM Clock Gating Register 2 (CCM_CCGR2)
DATA 4 0x020c4074 0xffffffff CCM Clock Gating Register 3 (CCM_CCGR3)
DATA 4 0x020c4078 0xffffffff CCM Clock Gating Register 4 (CCM_CCGR4)
DATA 4 0x020c407c 0xffffffff CCM Clock Gating Register 5 (CCM_CCGR5)
DATA 4 0x020c4080 0xffffffff CCM Clock Gating Register 6 (CCM_CCGR6)

DATA 4 0x020E04B4 0x000C0000 SW_PAD_CTL_GRP_DDR_TYPE SW GRP Register
DATA 4 0x020E04AC 0x00000000 SW_PAD_CTL_GRP_DDRPKE SW GRP Register
DATA 4 0x020E027C 0x00000030 SW_PAD_CTL_PAD_DRAM_SDCLK0_P SW PAD Control Register
DATA 4 0x020E0250 0x00000030 SW_PAD_CTL_PAD_DRAM_CAS_B SW PAD Control
DATA 4 0x020E024C 0x00000030 SW_PAD_CTL_PAD_DRAM_RAS_B SW PAD Control
DATA 4 0x020E0490 0x00000030 SW_PAD_CTL_GRP_ADDDS SW GRP Register
DATA 4 0x020E0288 0x00000030 SW_PAD_CTL_PAD_DRAM_RESET SW PAD Control
DATA 4 0x020E0270 0x00000000 SW_PAD_CTL_PAD_DRAM_SDBA2 SW PAD Control
DATA 4 0x020E0260 0x00000030 SW_PAD_CTL_PAD_DRAM_ODT0 SW PAD Control
DATA 4 0x020E0264 0x00000030 SW_PAD_CTL_PAD_DRAM_ODT1 SW PAD Control
DATA 4 0x020E04A0 0x00000030 SW_PAD_CTL_GRP_CTLDS SW GRP Register
DATA 4 0x020E0494 0x00020000 SW_PAD_CTL_GRP_DDRMODE_CTL SW GRP Register
DATA 4 0x020E0280 0x00000030 SW_PAD_CTL_PAD_DRAM_SDQS0_P SW PAD Control Register
DATA 4 0x020E0284 0x00000030 SW_PAD_CTL_PAD_DRAM_SDQS1_P SW PAD Control Register
DATA 4 0x020E04B0 0x00020000 SW_PAD_CTL_GRP_DDRMODE SW GRP Register
DATA 4 0x020E0498 0x00000030 SW_PAD_CTL_GRP_B0DS SW GRP Register
DATA 4 0x020E04A4 0x00000030 SW_PAD_CTL_GRP_B1DS SW GRP Register
DATA 4 0x020E0244 0x00000030 SW_PAD_CTL_PAD_DRAM_DQM0 SW PAD Control
DATA 4 0x020E0248 0x00000030 SW_PAD_CTL_PAD_DRAM_DQM1 SW PAD Control

DATA 4 0x021B001C 0x00008000 MMDC Core Special Command Register (MMDC_MDSCR)
DATA 4 0x021B0800 0xA1390003 MMDC PHY ZQ HW control register
DATA 4 0x021B080C 0x00000000 MMDC PHY Write Leveling Delay Control Register 0
DATA 4 0x021B083C 0x41490145 MMDC PHY Read DQS Gating Control Register 0
DATA 4 0x021B0848 0x40404546 MMDC PHY Read delay-lines Configuration Register
DATA 4 0x021B0850 0x4040524D MMDC PHY Write delay-lines Configuration Register
DATA 4 0x021B081C 0x33333333 MMDC PHY Read DQ Byte0 Delay Register
DATA 4 0x021B0820 0x33333333 MMDC PHY Read DQ Byte1 Delay Register
DATA 4 0x021B082C 0xf3333333 MMDC PHY Write DQ Byte0 Delay Register
DATA 4 0x021B0830 0xf3333333 MMDC PHY Write DQ Byte1 Delay Register
DATA 4 0x021B08C0 0x00921012 MMDC Duty Cycle Control Register (MMDC_MPDCCR)
DATA 4 0x021B08b8 0x00000800 MMDC PHY Measure Unit Register (MMDC_MPMUR0)
DATA 4 0x021B0004 0x0002002D MMDC Core Power Down Control Register (MMDC_MDPDC)
DATA 4 0x021B0008 0x00333030 MMDC Core ODT Timing Control Register (MMDC_MDOTC)
DATA 4 0x021B000C 0x676B52F3 MMDC Core Timing Configuration Register 0 (MMDC_MDCFG0)
DATA 4 0x021B0010 0xB66D8B63 MMDC Core Timing Configuration Register 1 (MMDC_MDCFG1)
DATA 4 0x021B0014 0x01FF00DB MMDC Core Timing Configuration Register 2 (MMDC_MDCFG2)
DATA 4 0x021B0018 0x00201740 MMDC Core Miscellaneous Register (MMDC_MDMISC)
DATA 4 0x021B001C 0x00008000 MMDC Core Special Command Register (MMDC_MDSCR)
DATA 4 0x021B002C 0x000026D2 MMDC Core Read/Write Command Delay Register (MMDC_MDRWD)
DATA 4 0x021B0030 0x006B1023 MMDC Core Out of Reset Delays Register (MMDC_MDOR)
DATA 4 0x021B0040 0x0000004F MMDC Core Address Space Partition Register (MMDC_MDASP)
DATA 4 0x021B0000 0x84180000 MMDC Core Control Register (MMDC_MDCTL)
DATA 4 0x021B001C 0x02008032 MMDC Core Special Command Register (MMDC_MDSCR)
DATA 4 0x021B001C 0x00008033 MMDC Core Special Command Register (MMDC_MDSCR)
DATA 4 0x021B001C 0x00048031 MMDC Core Special Command Register (MMDC_MDSCR)
DATA 4 0x021B001C 0x15208030 MMDC Core Special Command Register (MMDC_MDSCR)
DATA 4 0x021B001C 0x04008040 MMDC Core Special Command Register (MMDC_MDSCR)
DATA 4 0x021B0020 0x00000800 MMDC Core Refresh Control Register (MMDC_MDREF)
DATA 4 0x021B0818 0x00000227 MMDC PHY ODT control register (MMDC_MPODTCTRL)
DATA 4 0x021B0004 0x0002552D MMDC Core Power Down Control Register (MMDC_MDPDC)
DATA 4 0x021B0404 0x00011006 MMDC Core Power Saving Control and Status Register (MMDC_MAPSR)
DATA 4 0x021B001C 0x00000000 MMDC Core Special Command Register (MMDC_MDSCR)