BMS Analog Front End (AFE) Project Description

Responsible Engineers

Jarod Krane

High Level Project Objective

To develop a BMS that can monitor and passively balance lithium ion cells.

Purpose of the Project

The BMS is the heart of an electric vehicle, and is critical to the safety of the driver when using a lithium ion battery pack.

Deliverables

• High level system block diagram of BMS AFE boards (connections with each other, with battery pack, and with BMS master)
• BOM for all components needed to use BQ76PL455A IC
• Schematic for balancing/sensing section of AFE
• Schematic for IC peripherals (decoupling capacitors, power transistors…)
• Schematic for connections to battery cells
• Schematic for UART connection to BMS master
• Schematic for isolated differential communication to other AFEs
• PCB for entire AFE (2 layers within 100mmx100mm)
• Documentation on functionality and features
• This is a High Voltage PCB, a document must be created with screenshots demonstrating all the HV isolation rules followed

Steps to convert boards to top UART board

• Depopulate R10, R11, R20, R30

Steps to convert boards to downstream daisy-chained AFEs

• Populate R10, R11, R20, R30 (connecting RX, TX, VP, to VIO and wakeup to ground)
• Depopulate J1
• For unused cells on the final daisy chained board depopulate all components of the Vsense_EQ schematic of the corresponding unused cells. Short across all zener diode pads from top line to the highest used cell

REV 2 Schematics