Page Translation

In the second phase of address transformation, the 80386 transforms a linear address into a physical address. This phase of address transformation implements the basic features needed for page-oriented virtual-memory systems and page-level protection.

When is page translation in effect?

Ref (Chapter 5.2, Intel 80386 Programmer's Reference Manual)

Page translation step is optional. It is in effect only when the PG bit of CR0 is set.

What is a Page Frame?

Ref (Chapter 5.2.1, Intel 80386 Programmer's Reference Manual)

A page frame is a 4K-byte unit of contiguous addresses of physical memory. Pages begin on byte boundaries and are fixed in size.

How does linear address refer to physical address?

Ref (Chapter 5.2.2, Intel 80386 Programmer's Reference Manual)

A linear address refers indirectly to a physical address by specifying a page table, a page within that table, and an offset within that page.

What is the format of linear address?

Ref (Chapter 5.2.2, Intel 80386 Programmer's Reference Manual)

31           22 21           12 11             0
+--------------+---------------+---------------+
|     DIR      |      PAGE     |     OFFSET    |
+--------------+---------------+---------------+

• DIR - an index into a page directory;
• PAGE - an index into the page table determined by the page directory;
• OFFSET - an offset from the start of the page determined by the page table.

What is a Page Table?

Ref (Chapter 5.2.3, Intel 80386 Programmer's Reference Manual)

A page table is an array of 32-bit page specifiers. A page table is itself a page, and therefore contains 4 Kilobytes of memory or at most 1K 32-bit entries.

How page tables can span entire physical space of 80386?

Ref (Chapter 5.2.3, Intel 80386 Programmer's Reference Manual)

Two levels of tables are used to address a page of memory. At the higher level is a page directory. The page directory addresses up to 1K page tables of the second level.

A page table of the second level addresses up to 1K pages. All the tables addressed by one page directory, therefore, can address 1M pages (2^20). Because each page contains 4K bytes (2^12 bytes), the tables of one page directory can span the entire physical address space of the 80386 (2^20 x 2^12 = 2^32).

Where the current page directory address is stored?

Ref (Chapter 5.2.3, Intel 80386 Programmer's Reference Manual)

The physical address of the current page directory is stored in the CPU register CR3, also called the Page Directory Base Register (PDBR).

What is the format of page table entry?

Ref (Chapter 5.2.4, Intel 80386 Programmer's Reference Manual)

31                                  12 11                               0
+-------------------------------------+--------+----+--+--+----+--+--+--+
|                                     |        |    |  |  |    |U |R |  |
|          Page Frame Address         |  AVAIL |0 0 |D |A |0 0 |/ |/ |P |
|                                     |        |    |  |  |    |S |W |  |
+-------------------------------------+--------+----+--+--+----+--+--+--+
                                         ^           ^  ^       ^  ^  ^
                                         |           |  |       |  |  |
Available For Systems Programmers Use ___|           |  |       |  |  |
Dirty _______________________________________________|  |       |  |  |
Accessed _______________________________________________|       |  |  |
User / Supervisor ______________________________________________|  |  |
Read / Write ______________________________________________________|  |
Present ______________________________________________________________|

• Page Frame Address - specifies the physical starting address of a page. Because pages are loaded on 4K boundaries, the low-order 12-bits are always zero. In a page directory, the page frame address is the address of a page table. In a second-level page table, the page frame address is the address of the page frame that contains the desired memory operand.
• Present Bit - indicates whether a page table entry can be used in address translation. P=1 indicates the entry can be used. When P=0 in either level of page tables, the entry is not valid for address translation, and the rest of the entry is available for software use.
• Accessed and Dirty Bits - provide data about page usage in both levels of the page tables. With the exception of the dirty bit in a page directory entry, these bits are set by hardware; however, the processor does not clear any of these bits. Operating system is responsible for testing and clearing these bits.
• Read/Write and User/Supervisor Bits - are not used for address translation, but are used for page-level protection, which the processor performs at the same time as address translation.