CPU Registers CR4 - seporaitis/xv6-public GitHub Wiki

CR3 Register

What is the structure of CR4 register?


              31(63)                  23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
             -------------------------------------------------------------------------------------------------
             |                          |P |S |S |  |O |P |F |  |S |V |  |U |O |O |P |P |M |P |P |  |T |P |V |
             |         Reserved         |K |M |M |0 |S |C |S |0 |M |M |0 |M |S |S |C |G |C |A |S |D |S |V |M |
             |                          |E |A |E |  |X |I |G |  |X |X |  |I |X |F |E |E |E |E |E |E |D |I |E |
             |                          |  |P |P |  |S |D |S |  |E |E |  |P |M |X |  |  |  |  |  |  |  |  |  |
             -------------------------------------------------------------------------------------------------
                                         ^  ^  ^     ^  ^  ^     ^  ^     ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^
 Protection-Key-Enable Bit_______________|  |  |     |  |  |     |  |     |  |  |  |  |  |  |  |  |  |  |  |
 Supervisor Mode Access Prevention Bit______|  |     |  |  |     |  |     |  |  |  |  |  |  |  |  |  |  |  |
 Supervisor Mode Execution Prevention Bit _____|     |  |  |     |  |     |  |  |  |  |  |  |  |  |  |  |  |
 XSAVE and Processor Extended States Enable Bit______|  |  |     |  |     |  |  |  |  |  |  |  |  |  |  |  |
 PCID-Enable Bit________________________________________|  |     |  |     |  |  |  |  |  |  |  |  |  |  |  |
 FSGSBASE-Enable Bit_______________________________________|     |  |     |  |  |  |  |  |  |  |  |  |  |  |
 SMX-Enable Bit__________________________________________________|  |     |  |  |  |  |  |  |  |  |  |  |  |
 VMX-Enable Bit_____________________________________________________|     |  |  |  |  |  |  |  |  |  |  |  |
 User-Mode Instruction Prevention_________________________________________|  |  |  |  |  |  |  |  |  |  |  |
 OSXMMEXCPT (OS Support for Unmasked SI MD Floating-Point Exceptions)________|  |  |  |  |  |  |  |  |  |  |
 OSFXSR (OS Support for FXSAVE and FXRSTOR instructions)________________________|  |  |  |  |  |  |  |  |  |
 Performance-Monitoring Counter Enable_____________________________________________|  |  |  |  |  |  |  |  |
 Page Global Enable___________________________________________________________________|  |  |  |  |  |  |  |
 Machine Check Enable____________________________________________________________________|  |  |  |  |  |  |
 Physical Address Extension_________________________________________________________________|  |  |  |  |  |
 Page Size Extensions__________________________________________________________________________|  |  |  |  |
 Debugging Extensions_____________________________________________________________________________|  |  |  |
 Time Stamp Disable__________________________________________________________________________________|  |  |
 Protected Mode Virtual Interrupts______________________________________________________________________|  |
 Virtual-8086 Mode Extensions______________________________________________________________________________|
  • PKE (bit 22) - Protection-Key-Enable Bit - enables IA-32e paging to associate each linear address with a protection key. The PKRU register specifies, for each protection key, whether user-mode linear addresses with that protection key can be read or written. This bit also enables access to PKRU register using the RDPKRU and WRPKRU instructions.
  • SMAP (bit 21) - Supervisor Mode Access Prevention Bit
  • SMEP (bit 20) - Supervisor Mode Execution Prevention Bit
  • OSXSAVE (bit 18) - XSAVE and Processor Extended States Enable Bit - when set this flag indicates that the operating system supports the use of XGETBV, XSAVE and XRSTOR instructions by general software.
  • PCIDE (bit 17) - PCID-Enable Bit - enables process-context identifiers (PCIDs) when set.
  • FSGSBASE (bit 16) - FSGSBASE-Enable Bit - enables instructions RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
  • SMXE (bit 14) - SMX-Enable Bit - enables SMX operation when set.
  • VMXE (bit 13) - VMX-Enable Bit - enables VMX operation when set.
  • UMIP (bit 11) - User Mode Instruction-Prevention Bit - when set, the following instructions cannot be executed if CPL > 0: SGDT, SIDT, SLDT, SMSW, and STR. An attempt at such execution causes a general protection exception (#GP).
  • OSXMMEXCPT (bit 10) - OS Support for Unmasked SI MD Floating Point Exceptions - when set, indicates that the operating system supports the handling of unmasked SIMD floating-point exceptions through an exception handler that is invoked when a SIMD floating-point exception (#XM) is generated. The operating system or executive must explicitly set this flag. If this flag is not set, the processor will generate an invalid opcode exception (#UD) whenever it detects an unmasked SIMD floating-point exception.
  • OSXFXSR (bit 9) - OS Support for FXSAVE and FXSTOR instructions - when set, indicates to software that the operating system supports the use of the FXSAVE and FXSTOR instructions.
  • PCE (bit 8) - Performance Monitoring Counter Enable - enables execution of RDPMC instruction of programs or procedures running at any protection level when set; RDPMC instruction can be executed only at protection level 0 when clear.
  • PGE (bit 7) - Page Global Enable - enables the global page feature when set. The global page feature allows frequently used or shared pages to be marked as global to all users.
  • MCE (bit 6) - Machine Check Enable - enables machine-check exception when set.
  • PAE (bit 5) - Physical Address Extension - when set, enables paging to produce physical addresses with more than 32 bits. When clear, restricts physical addresses to 32 bits. PAE must be set before entering IA-32e mode.
  • PSE (bit 4) - Page Size Extensions - enables 4-MByte pages with 32-bit paging when set; restricts 32-bit paging to pages of 4-KBytes when clear.
  • DE (bit 3) - Debugging Extensions - references to debug registers DR4 and DR5 cause an undefined opcode (#UD) exception to be generated when set; when clear, processor aliases references to registers DR4 and DR5 for compatibility with software written to run on earlier IA-32 processors.
  • TSD (bit 2) - Time Stamp Disable - restricts the execution of the RDTSC instruction to procedures running at privilege level 0 when set; allows RDTSC instruction to be executed at any privilege level when clear.
  • PVI (bit 1) - Protected-Mode Virtual Interrupts - enables hardware support for a virtual interrupt flag (VIF) in protected mode when set; disables the VIF flag in protected mode when clear.
  • VME (bit 0) - Virtual-8086 Mode Extensions - enables interrupt- and exception-handling extensions in virtual-8086 mode when set; disables the extensions when clear.