Interrupts and Exceptions

What is an interrupt and exception?

Ref: (5.1, Intel 64 and IA-32 Architectures Software Developer's Manual)

Interrupts and exceptions are events that indicate that a condition exists somewhere in the system, the processor, or within the currently executing program or task that requires the attention of a processor.

When is interrupt handler invoked?

Ref: (5.1, Intel 64 and IA-32 Architectures Software Developer's Manual)

Interrupts and exceptions typically result in a forced transfer of execution from the currently running program or task to a special software routine or task called an interrupt handler.

What does 'handling the interrupt or exception' mean?

Ref: (5.1, Intel 64 and IA-32 Architectures Software Developer's Manual)

The action taken by a processor in response to an interrupt or exception is referred to as servicing or handling the interrupt or exception.

What can generate interrupts?

Ref: (5.1, Intel 64 and IA-32 Architectures Software Developer's Manual)

System hardware uses interrupts to handle events external to the processor, such as requests to service peripheral devices.

Software can also generate interrupts by executing INT n instruction.

When do exceptions occur?

Ref: (5.1, Intel 64 and IA-32 Architectures Software Developer's Manual)

Exceptions occur when the processor detects an error condition while executing an instruction, such as division by zero. The processor detects a variety of error conditions including protection violations, page faults, and internal machine faults.

What are exception and interrupt vectors?

Ref: (5.2, Intel 64 and IA-32 Architectures Software Developer's Manual)

A unique identification number assigned to each interrupt and exception condition to aid in handling them.

What is the allowable range of vector numbers?

Ref: (5.2, Intel 64 and IA-32 Architectures Software Developer's Manual)

The allowable range for vector numbers is 0-255.

Vectors in the range 0-31 are reserved by the Intel 64 and IA-32 architectures for architecture-defined exceptions and interrupts.

Vectors in the range 32-255 are designated as user-defined interrupts and are not reserved by the Intel 64 and IA-32 architecture. These interrupts are generally assigned to external I/O devices to enable those devices to send interrupts to the processor through one of the external hardware interrupt mechanisms.

What are the sources of interrupts?

1. External (hardware generated) interrupts
2. Software-generated interrupts.

How are external interrupts received?

Ref: (5.3.1, Intel 64 and IA-32 Architectures Software Developer's Manual)

External interrupts are received through pins on the processor or through the local API C.

What are Maskable Hardware Interrupts?

Ref: (5.3.2, Intel 64 and IA-32 Architectures Software Developer's Manual)

Any external interrupt that is delivered to the processor by means of the INTR pin or through the local API C is called a maskable hardware interrupts.

Maskable hardware interrupts that can be delivered through the INTR pin include all IA-32 architecture defined interrupt vectors 0-255; those that can be delivered through the local API C include interrupt vectors 16-255.

What are Software-Generated Interrupts?

Ref: (5.3.3, Intel 64 and IA-32 Architectures Software Developer's Manual)

The INT n instruction permits interrupts to be generated from within software by supplying an interrupt vector number as an operand.

Exceptions

What can be sources of exceptions?

Ref: (5.4, Intel 64 and IA-32 Architectures Software Developer's Manual)

• Processor-detected program-error exceptions
• Software-generated exceptions.
• Machine-check exceptions.

How are program-error exceptions generated?

Ref: (5.4.1, Intel 64 and IA-32 Architectures Software Developer's Manual)

The processor generates one or more exceptions when it detects program errors during the execution in an application program or the operating system or executive.

How are software exceptions generated?

Ref: (5.4.2, Intel 64 and IA-32 Architectures Software Developer's Manual)

The INTO, INT 3, and BOUND instructions permit exceptions to be generated in software. These instructions allow checks for exception conditions to be performed at points in the instruction stream.

What is the limitation of using INT n for emulating exceptions?

Ref: (5.4.2, Intel 64 and IA-32 Architectures Software Developer's Manual)

The INT n instruction can be used to emulate exceptions in software; but there is a limitation. If INT n provides a vector for one of the architecturally-defined exceptions, the processor generates an interrupt to the correct vector (to access the exception handler), but does not push an error code on the stack. This may cause return from the handler to wrong location.

Exception classification

How are exceptions classified?

Ref: (5.5, Intel 64 and IA-32 Architectures Software Developer's Manual)

• Faults
• Traps
• Aborts

What are faults?

Ref: (5.5, Intel 64 and IA-32 Architectures Software Developer's Manual)

A fault is an exception that can generally be corrected and that, once corrected, allows the program to be restarted with no loss of continuity.

How does fault mechanism work?

Ref: (5.5, Intel 64 and IA-32 Architectures Software Developer's Manual)

When a fault is reported, the processor restores the machine state to the state prior to the beginning of execution of the faulting instruction. The return address (saved contents of the CS and EIP registers) for the fault handler points to the faulting instruction, rather than to the instruction following the faulting instruction.

What are traps?

Ref: (5.5, Intel 64 and IA-32 Architectures Software Developer's Manual)

A trap is an exception that is reported immediately following the execution of the trapping instruction.

How does trapping mechanism work?

Ref: (5.5, Intel 64 and IA-32 Architectures Software Developer's Manual)

Traps allow execution of a program or task to be continued without loss of program continuity. The return address for the trap handler points to the instruction to be executed after the trapping instruction.

What are aborts?

Ref: (5.5, Intel 64 and IA-32 Architectures Software Developer's Manual)

An abort is an exception that does not always report the precise location of the instruction causing the exception and does not allow a restart of the program or task that caused exception. Aborts are used to report severe errors, such as hardware errors and inconsistent or illegal values in system tables.

Non-Maskable Interrupts

What are Nonmaskable Interrupts (NMIs)?

Ref: ( Wikipedia )

A non-maskable interrupt (NMI) is a hardware interrupt that standard interrupt-masking techniques in the system cannot ignore.

How are non-maskable interrupts generated?

Ref: (5.7, Intel 64 and IA-32 Architectures Software Developer's Manual)

• External hardware asserts the NMI pin.
• The processor receives a message on the system bus or the API C serial bus with a delivery mode NMI.

How does NMI handling mechanism work?

Ref: (5.7, Intel 64 and IA-32 Architectures Software Developer's Manual)

When the processor receives a NMI from either of the sources, the processor handles it immediately by calling the NMI handler pointed to by interrupt vector number 2. The processor also invokes certain hardware conditions to insure that no other interrupts, including NMI interrupts, are received until the NMI handler has completed executing.

Enabling and Disabling Interrupts

How can interrupts be disabled?

Ref: (5.8, Intel 64 and IA-32 Architectures Software Developer's Manual)

The IF flag in EFLAGS register can disable the servicing of maskable hardware interrupts received on the processor's INTR pin or through the local API C.

When does processor inhibits interrupts?

Ref: (5.8.1, Intel 64 and IA-32 Architectures Software Developer's Manual)

When the IF flag is clear, the processor inhibits interrupts; when IF flag is set, interrupts are processed as normal external interrupts.

Can Non-Maskable Interrupts be disabled with IF flag?

Ref: (5.8.1, Intel 64 and IA-32 Architectures Software Developer's Manual)

The IF flag does not affect non-maskable interrupts delivered to the NMI pin or delivery mode NMI messages delivered through the local API C, nor does it affect processor generated exceptions.

How can IF flag be controlled?

Ref: (5.8.1, Intel 64 and IA-32 Architectures Software Developer's Manual)

The IF flag can be set or cleared with STI (set interrupt-enable flag) and CLI (clear interrupt-enable flag) instructions, respectively.

How does processor mask exceptions and interrupts when switching stacks?

Ref: (5.8.3, Intel 64 and IA-32 Architectures Software Developer's Manual)

To switch to a different stack segment, software often uses a pair of instructions, for example:

    mov ss, ax
    mov esp, stacktop

If an interrupt or exception occurs after the segment selector has been loaded into the SS register but before the ESP register has been loaded, these two parts of the logical address into the stack space are inconsistent for the duration of the interrupt or exception handler.

To prevent this situation, the processor inhibits interrupts, debug exceptions, and single-step trap exceptions after either a mov ss instruction or a pop ss instruction, until the instruction boundary following the next instruction is reached.

If the LSS instruction is used to modify the contents of the SS register, this problem does not occur.

Priorities among Exceptions and Interrupts

Priority	Description
1 (Highest)	Hardware reset and machine checks
2	Trap on Task Switch
3	External Hardware Interventions
4	Traps on the Previous Instruction
5	Nonmaksable Interrupts (NMI)
6	Maskable Hardware Interrupts
7	Code Breakpoint Fault
8	Faults from Fetching Next Instruction
9	Faults from Decoding Next Instruction
10 (Lowest)	Faults on Executing an Instruction

Interrupt Descriptor Table

What is Interrupt Descriptor Table

Ref: (5.10, Intel 64 and IA-32 Architectures Software Developer's Manual)

An array of 8-byte descriptors.

What is IDT structure?

Interrupt number is an index into IDT.

Ref: (20.1.4, Intel Software Developer's Manual)

The entry in the IDT provides a pointer to an interrupt-or-exception-handler procedure. (The pointer consists of a segment selector for a code segment and a 16-bit offset into the segment.) The processor performs the following actions to make an implicit call to the selected handler:

1. Pushes the current values of the CS and EIP registers onto the stack. (Only the 16-least-significant bits of the EIP register are pushed.)
2. Pushes the low-order 16 bits of the EFLAGS register onto the stack.
3. Clears the IF flag in the EFLAGS register to disable interrupts.
4. Clears TF, RF, and AC flag, in the EFLAGS register.
5. Transfers program control to the location specified in the IDT.

An IRET instruction at the end of the handler procedure reverses these steps to return program control to the interrupted program.

Interrupt Descriptor Table is an array of 4-byte entries. Each entry consists of a far pointer to a handler procedure.

                              __________________________
                             |        Entry 255         |
                             |__________________________| 1020
                             |           ...            |
                             |__________________________| ...
                             |         Entry 2          |
                             |__________________________| 8
                             |         Entry 1          |
                          __ |__________________________| 4
 Interrupt Vector 0 ---> |   |____ Segment Selector ____| 2
                         |__ |_________ Offset _________| 0  <--
                             15                         0      |
                                                             IDTR