8.Test Case - sagarpattar005/apb_avip GitHub Wiki
In the test, there is virtual sequence and in virtual sequence, sequences are there, sequence_item get started in sequences, sequences will start in virtual sequence and virtual sequence will start in Test.
Fig 8.1 Test flow
Fig 8.2: APB test cases flow chart
| Variables | Type | Description |
|---|---|---|
| pselx | bit | Master asserts the pselx to select the slave device |
| pwrite | enum | Pwrite signal decides whether write data transfer happens from the master side or read data transfer happens to the master. |
| paddr | bit | Address. This is the APB address bus. It can be up to 32 bits wide and is a data access or an instruction access. |
| pprot | enum | Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access. |
| penable | bit | Enable.This signal indicates the second and subsequent cycle of an APB transfer. |
| pwdata | bit | Write data. This bus is driven by the peripheral bus bridge unit during the write cycle when pwrite is HIGH. This bus can be up to 32 bits wide. |
| pstrb | enum | Write strobes. This signal indicates when byte lanes to update during a write transfer. There is one write strobe for each eight bits of the write data bus. Therefore, pstrb[n] corresponds to pwdata[(8n+7):(8n)]. Write strobes must not be active during a read transfer. |
| pready | bit | Ready. The Slave uses this signal to extend an APB transfer. |
| prdata | bit | Read Data.The selected slave drives this bus during read cycles when pwrite is LOW. This bus can be up to 32-bits wide. |
| pslverr | enum | This signal indicates a transfer failure. APB peripherals are not required to support the pslverr pin. This is true for both existing and new APB peripheral designs. Where a peripheral does not include this PIN then the appropriate input to the APB bridge is tied LOW. |
Master_tx class is extended from the uvm_sequence_item holds the data items required to drive stimulus to dut.
Declared all the variables (pselx, paddr, pwrite, pwdata, pready pslverr, pprot, pstrobe).
Constraint declared for slave select and data transfer based on transfer size.
8.3: Constraint for pselx and transfer_size
| Constraint | Description |
|---|---|
| pselx_c1 | Declaring constraint for to select one slave at a time |
| pselx_c2 | Declaring constraint for pselx should be in specified range |
| transfer_size_c4 | This constraint is used to decide the pwdata based on the transfer size. (whether it is 8bit, 16bit, 24bit etc..) |
Table 8.3.2 Describing constraint for pselx and transfer size
Fig 8.4: do_compare method
Fig 8.5: do_copy method
Fig 8.6: do_print method
Slave_tx class is extended from the uvm_sequence_item holds the data items
required to drive stimulus to dut
Declared all the variables (pselx, paddr, pwrite, pwdata, pready, pslverr, pprot, pstrobe)
A UVM Sequence is an object that contains a behavior for generating stimulus. A sequence generates a series of sequence_item’s and sends it to the driver via sequencer, Sequence is written by extending the uvm_sequence.
| Method | Description |
|---|---|
| new | Creates and initializes a new sequence object |
| start_item | This method will send the request item to the sequencer, which will forward it to the driver |
| req.randomize() | Generate the transaction(seq_item). |
| finish_item | Wait for acknowledgement or response |
Table 8.1. Sequence methods
| Sections | Master sequences | Slave sequences | Description |
|---|---|---|---|
| base_seq | apb_base_master_seq | apb_base_slave_seq | Base class is extended from uvm_ sequence and parameterized with transaction (master_ tx, slave_ tx) |
| Data transfers | apb_8b_write_master_seq | apb_8b_write_slave_seq | Extended from base sequence. Based on a request from the driver, the task will drive the transactions. In between start_ item and finish_ item using inline constraint and randomizing the req with the transfer size is BIT_8 and selecting number of slaves |
| apb_16b_write_master_seq | apb_16b_write_slave_seq | Extended from base sequence. Based on a request from the driver, the task will drive the transactions. In between start_ item and finish_ item using inline constraint and randomizing the req with the transfer size is BIT_16 and selecting number of slaves | |
| apb_24b_write_master_seq | apb_24b_write_slave_seq | Extended from base sequence. Based on a request from the driver, the task will drive the transactions. In between start_ item and finish_ item using inline constraint and randomizing the req with the transfer size is BIT_24 and selecting number of slaves |
Table 8.2. Describing master and slave sequences
In master_seq body creating req and start item will start seq and randomizing the req with inline constraint and selecting slave then print req followed by finish item.
Fig 8.9: Slave seq body method
A virtual sequence is a container to start multiple sequences on different sequencers in the environment. This virtual sequence is usually executed by a virtual sequencer which has handles to real sequencers. This need for a virtual sequence arises when you require different sequences to be run on different environments.
Virtual sequence base class is extended from uvm_sequence and parameterized with uvm_transaction. Declaring p_sequencer as macro , handles virtual sequencer and master, slave sequencer and environment config.
Fig 8.10: Virtual base sequence
In virtual sequence body method,Getting the env configurations and Dynamic casting of p_sequencer and m_sequencer. Connect the master sequencer and slave sequencer in sequencer with local master sequencer and slave sequencer.
Fig 8.11: Virtual base sequence body
In the virtual sequence body method, creating master and slave sequence handles and starts the slave sequence within fork join_none and master sequence within repeat statement.
Fig 8.12:Virtual 8bit sequence body
| Sections | Virtual sequences | Description |
|---|---|---|
| Data transfer | apb_virtual_8b_write_seq | Inside the 8bit virtual sequence, extending from base class.Declaring handles of sequences and inside body method constructing handles of sequence. Configuring the master and slave sequencers. |
| apb_virtual_16b_write_seq | Inside the 16bit virtual sequence, extending from base class.Declaring handles of sequences and inside body method constructing handles of sequence. Configuring the master and slave sequencers. | |
| apb_virtual_24b_write_seq | Inside the 24bit virtual sequence, extending from base class.Declaring handles of sequences and inside body method constructing handles of sequence. Configuring the master and slave sequencers. |
Table 8.3. Describing virtual sequences