Table of Contents Combined i186/Z80 backend design Abstract: 1 Motivation 2 Processor descriptions 2.1 Zilog Z80 2.2 Nintendo GBZ80 2.3 Intel i186 2.4 Toshiba TLCS-900H 3 Common features 3.1 Stack 3.2 Registers 3.3 Memory 4 Design 4.1 Basics 4.2 Register allocator 4.3 Code generator

The primary motivation is to add a i186 backend to SDCC, and in the process come to understand register allocation. The secondary goal is to attempt to combine the common parts from the Z80 and i186 backends to make both easier to maintain. In the 'would be nice' category is adding support for the Toshiba TLCS-900H.

Name	Parts	Notes
AF	A	Accumulator and flags. Unusable as a pair.
BC	B, C
DE	D, E
HL	H, L
IX	None	Index register.
IY	None	Index register.

The Z80 also has a switchable alternate register set AF', BC', DE', and HL' which are not accessible directly. It is assumed that it is too hard to track these to make it worthwhile. IX and IY can be split at the byte level by using undocumented instructions. While this would make them more usable as general purpose registers, it is ignored for compatibility.

The GBZ80 is basically a Z80 less the index registers and the alternate register set.

Name	Parts	Notes
AF	A	Accumulator and flags. Unusable as a pair.
BC	B, C
DE	D, E
HL	H, L

Name	Parts	Notes
AX	AH, AL	Accumulator.
BX	BH, BL
CX	CH, CL
DX	DH, DL
DI	None	Destination Index.
SI	None	Source Index.
BP	None	Base pointer.

Note that the segment registers CS, DS, ES, and SS are not listed. For simplicity only tiny mode is supported. Tiny mode is where both the data and code exist in one segment, such that CS = DS. This allows constant data stored in the code segment to be accessed in the same method as data. This may cause trouble later if far mode is needed.

The 900H seems to be inspired by the Z80. It is listed as a 16 bit device, but most of the registers are 32 bits wide.

Name	Parts	Notes
XWA	WA, W, A	Accumulator
XBC	BC, B, C
XDE	DE, D, E
XHL	HL, H, L
XIX	IX
XIY	IY
XIZ	IZ

All registers can act as either an index base or an index offset. The offset is limited to sixteen bits. Apparently XIX, XIY, and XIZ can be split at the byte level. For simplicity this is ignored.

The stack grows downwards. All push operations are pre-decrement. All but the GBZ80 have a base pointer register that can be used along with an offset to access local variables and parameters. The GBZ80 and Z80 both have problems with more than 127 bytes of local variables due to their offset being a INT8.

All contain a reasonable but small number of registers. All have some special purpose registers which can either be handled separately or ignored. All general purpose registers can be split at the byte and word level, but doing so may make the rest of the register unavailable.

All have a 64k address space. However this should not be assumed to make far support easier later.

The design is mainly stack based, such that all local variables and parameters go onto the stack. Compare with the mcs51 backend which overlays variables onto a shared static area.

All stack access goes through the base pointer register (BP). The stack frame consists of the parameters pushed right to left, the return context, and then local variables. SP points to the base of the local variables. BP points to the bottom of the return context and hence to just above the top of the local variables. Note that as the stack grows down the parameters appear with the left most parameter at the lowest address.

A scratch register will be available for any sub operation to use and will be valid only within that sub operation. The accumulator is also unavailable. Return values are normally returned in the scratch register and accumulator.

Name	i186	Z80	GBZ80	900H
Base pointer	BP	IX	HL	XIX
Scratch	BX	HL	DE	XHL
Return	BX, AX	HL, IY	DE, HL	XHL
Available	CX, DX	BC, DE	BC	XBC, XDE
Ignored	SI, DI	IY	None	XIY, XIZ

The current Z80 and mcs51 register allocators perform these steps:

1. Pack each basic block by removing straight assignments and marking remat. iTemps.
2. Set the number of registers required for each live range based on the type and size of the live range.
3. Assign registers to each segment by deassigning registers and stack locations for any just expired iTemps, skipping any instructions which don't need registers, and spilling and assigning registers to the result of this tuple.
4. Create the register mask for this segment.

Optimisations include assigning into the accumulator or the scratch register where possible. This requires knowledge of what the code generator touches for a given instruction.

The first generation register allocator will only pack assignments and mark remat. variables. Only the register management is processor specific. The allocator may ask for a given size register or if a given size register is available. Note that only whole registers may be returned. For example, allocation will fail if a sixteen bit register is requested and no pair is available, even two eight bit registers are available. Note that on the Z80, GBZ80, and i186 a request for a 32 bit register will always fail.

The possible operations are:

• NOT - Logical not. 0 -> 1, others -> 0.
• CPL - Bitwise complement.
• UMINUS - Unary minus. result = 0 - left.
• IPUSH - Push immediate onto the stack.
• CALL - Call a function.
• PCALL - Call via pointer.
• FUNCTION - Emit the function prelude.
• ENDFUNCTION - Emit the function prologue.
• RET - Load the return value and jump to end of function.
• LABEL - Generate a local label.
• GOTO - Jump to a local label.
• Arithmitic - , -, *, /, %.
• Comparison - LT, GT, LEQ, GEQ, !=, =.
• Logical - &&, ||
• Binary - AND, OR, XOR.
• Shift - RRC, RLC, LSR, LSL.
• Pointer - Set and Get.
• Assign.
• IF jump.
• Misc - Jump table, cast, address of.