Video Generator - rosco-pc/propeller-wiki GitHub Wiki

Each cog has a video generator module that facilitates transmitting video image data at a constant rate. There are two registers (VCFG and VSCL) and one instruction (WAITVID) which provide control and access to the video generator. The timing signal for the Video Generator is provided by Counter A running in a PLL mode (PLLA). The PLLB of the cog is used to generate the broadcast frequency; whether this is generated depends on if PLLB is running and the values of VMode and VPins.

The Video Generator should be initialized by first starting Counter A, setting the Video Scale Register, setting the Video Configuration Register, then finally providing data via the WAITVID instruction. Failure to properly initialize the Video Generator by first starting PLLA will cause the cog to indefinitely hang when the WAITVID instruction is executed. DIRA must also be correctly set to permit output on the configured pins. While all public registers in a cog are reset when a cog is initialised this doesn't apply to the frame counter. Meaning its initial value depends on chip and cog used, in other words it's unknown. Which also means that the initial WAITVID spends a maximum of 4K PLLA cycles before it reloads VSCL (the first known value, VSCL is loaded when the frame counter reaches zero).

While the Video Generator was created to display video signals, its potential applications are much more diverse. The Composite Video mode can be used to generate phase-shift keying communications of a granularity of 16 or less and the VGA mode can be used to generate any bit pattern with a fully settable and predictable rate.

VCFG – Video Configuration Register The Video Configuration Register contains the configuration settings of the video generator and consists of several sub-fields: VCFG[30..29] VMode (video mode) field selects the mode (VGA or composite) and pins used for composite mode

VCFG[28] CMode (color mode) selects 0 = two-color mode (pixel data is 32 bits by 1 bit and only colors 0 or 1 are used) or 1 = four-color mode (pixel data is 16 bits by 2 bits, and colors 0 through 3 are used) VCFG[27] Chroma1 (broadcast color mode) 1 = enables or 0 = disables chroma (color) on the broadcast signal. VCFG[26] Chroma0 (baseband color mode) 1 = chroma (color) on VPin 0:2 / 4:6 or 0 = chroma (color) on VPin 3 / 7 VCFG[25..23] AuralSub selects COGID of FM audio output for broadcast output on VPins 3 / 7 VCFG[11..9] VGroup selects group of 8 I/O pins used for output (i.e. 3 = P24..P31) VCFG[7..0] VPins output mask for signals

VSCL – Video Scale Register The Video Scale Register sets the rate at which video data is generated and has two sub-fields:

VSCL[19.12] PixelClocks the number of PLLA clocks before the next pixel is shifted out by the video generator module. A value of 0 for this field is interpreted as 256. VSCL[0..11] FrameClocks the number of PLLA clocks that will elapse before the Video Generator Pixel and Color registers and Frame and Pixel counters are reloaded. A value of 0 for this field is interpreted as 4096. It is recommended FrameClocks be an integer multiple of PixelClocks. Since the pixel data is either 16 bits by 2 bits, or 32 bits by 1 bit (meaning 16 pixels wide with 4 colors, or 32 pixels wide with 2 colors, respectively), the FrameClocks is typically 16 or 32 times that of the PixelClocks value.

WAITVID Command/Instruction The WAITVID instruction is the delivery mechanism for data to the cog’s Video Generator hardware. Since the Video Generator works independently from the cog itself, the two must synchronize each time data is needed for the display device. The frequency at which this occurs is dictated by the frequency of PLLA and the FrameClocks field in the Video Scale Register. The cog must have new data available before the moment the Video Generator needs it. The cog uses WAITVID to wait for the right time and then “hand off” this data to the Video Generator. The WAITVID instruction blocks until the Frame counter expires. If the Frame counter expires before the WAITVID instruction blocks then the Video Generator Pixel and Color registers will be loaded with the current contents of the Source and Destination buses, leading to unpredictable output.

The WAITVID instruction passes two longs of data to the Video Generator which are loaded into the Pixel and Color registers. The Colors parameter is a 32-bit value containing four 8-bit color values (although only Color[15..8] and Color[7..0] are used in 2 color mode).

The Pixels parameter describes the pixel pattern to display. The Pixel data is shifted out least significant bits (LSB) first. If CMode = 0 (two color mode), Pixels is a 32x1 bit pattern where each bit specifies which of the two color patterns in the lower 16 bits of Colors should be output to the pins. If the FrameClocks value is greater than 32 times PixelClocks value then the most significant bit is repeated until FrameClocks PLLA cycles have occurred. If CMode = 1 (four color mode), Pixels is a 16x2 bit pattern where each 2-bit pixel is an index into Colors on which data pattern should be presented to the pins. If the FrameClocks value is greater than 16 times the PixelClocks value then the two most significant bits are repeated until FrameClocks PLLA cycles have occurred.

VGA output For VGA mode, each 8-bit color value is written to the pins specified by the VGroup and VPins field. On the Propeller Demo Board VPin 0 is Horizontal Sync, VPin 1 is Vertical Sync, VPin 2:3 is Blue, VPin 4:5 is Green and VPin 6:7 for 64 color VGA output.

Composite output For composite video each 8-bit color value is composed of 3 fields. Bits 0-2 are the luminance value of the generated signal. Bit 3 is the modulation bit which dictates whether the chroma information will be generated and bits 4-7 indicate the phase angle of the chroma value. When the modulation bit is set to 0, the chroma information is ignored and only the luminance value is output to pins. When the modulation bit is set to 1 and Chroma0/Chroma1 is 1 then the luminance value is modulated ± 1 with a phase angle set by bits 4-7. In order to achieve the full resolution of the chroma value, PLLA should be set to 16 times the modulation frequency (in composite video this is called the color-burst frequency).

Broadcast output Normally, for baseband, the three video resistors form a 3-bit DAC that is 1V-peak under a 75-ohm load. Outputs levels range from #0 to #7 (0 to 1V in ~125mv steps).

For broadcast, those baseband 0-to-7 levels are modulated at the broadcast frequency (CTRB's PLL) in the following pattern: 0 -> 0,7 (bottom of sync = max AC amplitude) 1 -> 1,7 2 -> 1,6 3 -> 2,6 4 -> 2,5 5 -> 3,5 6 -> 3,4 7 -> 4,4 (top of white level = min AC amplitude) So, this is away to get 8 AC levels from what would otherwise be an 8-level DC DAC.

For aural subcarrier, an extra resistor can be added after relative pins 0-2, on relative pin 3. In the VCFG register, you can select which other COG's CTRA PLL output will be modulated along with the video to provide the aural subcarrier. The Video Generator XOR's the other COG's CTRA PLL with its own CTRB PLL and outputs that to the fourth pin. For NTSC, this other-cog's PLL output must be a 100KHz-bandwidth 4.5MHz-center FM signal.

The key to getting good broadcast video is to select a FRQB value that has one's in a span of only 2-3 bits. This keeps the NCO jitter pattern high-frequency enough that the CTRB PLL can filter it out. For example, if you're running the Propeller at 80MHz, you can use $0C00_000 (3/4 of 80 MHz) to generate a very clean 60MHz, which is just below channel 3 in the US. Most TV receiver's PLLs will lock onto this when you go to channel 3.