Propeller 2 Instructions - rosco-pc/propeller-wiki GitHub Wiki

The new chip will have all the the existing instructions with the same binary layout. New instructions have been mapped into the unused slots. (Reference = Chip Gracey Post)

• MUL - multiply instruction. This is the only post I could find with any mention of the multiply.
• Pre/post increment/decrement RDxxxx/WRxxxx enhancement. New SETPTRA/B instructions and PTRA/B registers. See this post for details.
• REP[x,y] - repeat y instructions x times. The repeated instructions will be 2 instructions after this one due to pipelining. See this post for details.
• SWAPZC D - swap the Z and C flags with the 0 and 1 bits in D. See this post for details. (this may be out based on some later discussion)
• JMPD/JMPRETD - delayed jump. The jump would occur two instructions later. This allows the two instructions already in the pipeline to finish and the new instruction after the jump to pipeline in without a stall. See this post for details.
• RDQUADL/WRQUADL - read/write 4 longs to/from HUB memory. See this post for details (also just above it where he first mentions 8 longs but changes to 4).
• ??? - Instructions to read/write a 256 word (16bit) color look up table (CLUT). This post mentions it. This post says that this memory will also be usable as 128 longs of just general data storage.

Other related info: In this post, Chip mentions a divider circuit. The concept is that you would write your values to registers and then some number of clocks later read the results back out. This same concept is mentioned for square root elsewhere in the same thread.

This post mentions: CORDIC, MAC/MACS, REPeat, indirect register addressing, and hub memory pointers. Chip mentions in other posts some instructions called SETINDA/B, and associated INDA/B registers. These are the "indirect register addressing" feature. This post has some more info on these. He, also, mentions the PTRA/B and SETPTRA/B instructions when talking about the post/pre increment/decrement feature enhancement to RDxxxx/WRxxxx. These are the "hub memory pointers" feature. It's unknown at this time if the PTRA/B and INDA/B registers are just more special registers at the end of cog memory (most likely) or if they are something new.