Cog RAM - rosco-pc/propeller-wiki GitHub Wiki

Cog RAM is the memory local to each Cog. It consists of 496 longs of general purpose RAM for code and data plus another 16 longs as special purpose registers. Which gives each COG 512 longs total.

The general purpose memory is addressed from $000 and continuing to $1EF. The 16 special purpose registers are mapped from $1F0 to $1FF (see below).

Most of the instructions will manipulate the entire 32 bits at the given address. With the exception being the self-modifying instructions MOVS, MOVD, MOVI, CALL or JMPRET.

• MOVS allows the bottom 9 bits [B8 -> B0] of a Cog memory location to be modified without affecting other bits.
• MOVD allows the next 9 bits [B17 -> B9] to be modified.
• MOVI allows the most significant 9 bits [B31 -> B23] to be modified.
• CALL and JMPRET instructions will also modify the bottom 9 bits [B8 -> B0] of the RET instruction which relates to the subroutine being called to facilitate a return from Assembler Subroutines.

Bits 31 to 23	22 to 18	17 to 9	8 to 0
Instruction		Destination	Source
MOVI		MOVD	MOVS, CALL, or JMPRET

Special purpose registers

Address	Name	Type	Description
$1F0	PAR	Read-Only	Boot parameter
$1F1	CNT	Read-Only	System Counter
$1F2	INA	Read-Only	Input states for P31-P0
$1F3	INB	Read-Only	Input states for P63-P32*
$1F4	OUTA	Read/Write	Output States for P31-P0
$1F5	OUTB	Read/Write	Output states for P63-P32*
$1F6	DIRA	Read/Write	Direction States for P31-P0
$1F7	DIRB	Read/Write	Direction States for P63-P32*
$1F8	CTRA	Read/Write	Counter A Control
$1F9	CTRB	Read/Write	Counter B Control
$1FA	FRQA	Read/Write	Counter A Frequency
$1FB	FRQB	Read/Write	Counter B Frequency
$1FC	PHSA	Read/Write	Counter A Phase
$1FD	PHSB	Read/Write	Counter B Phase
$1FE	VCFG	Read/Write	Video Configuration
$1FF	VSCL	Read/Write	Video Scale

* Not implemented on the Propeller P8X32 chip.