RZG2LC‐SMARC Sample and Demo hardware configuration - renesas/zephyr GitHub Wiki

Followings are hardware connection and test samples for RZ/G2LC-SMARC, for more detail on 1st setup hardware connection, please visit RZ/G2L Group, RZ/G2LC Group User's Manual: Hardware and RZ/G2L, RZ/G2LC, RZ/G2UL, RZ/G3S Getting Started with Flexible Software Package

Default HW configuration

HW	Configurations	Remark
SW11[1:4]	OFF, OFF, OFF, ON	Boot mode 3(QSPI Boot (1.8V) Mode)
SW1-1	OFF	JTAG Debug mode

The UART port is accessed by connecting Pmod USBUART to the upper side of PMOD 1.

Hardware connection for UART samples

• echo_bot (samples/drivers/uart/echo_bot):

  • Hardware configuration: No additional connection.
  • Build command: west build -p always -b rzg2lc_smarc/r9a07g044c22gbg/cm33 samples/drivers/uart/echo_bot

• zTest uart_basic_api (tests/drivers/uart/uart_basic_api):

  • Hardware configuration: No additional connection.
  • Build command: west build -p always -b rzg2lc_smarc/r9a07g044c22gbg/cm33 tests/drivers/uart/uart_basic_api

Hardware connection for GPIO samples

• zTest gpio_api_1pin (tests/drivers/gpio/gpio_api_1pin):

  • Hardware configuration: No additional connection
  • Build command: west build -p always -b rzg2lc_smarc/r9a07g044c22gbg/cm33 tests/drivers/gpio/gpio_api_1pin

• zTest gpio_basic_api (tests/drivers/gpio/gpio_basic_api):

  • Hardware configuration:

    • Wire P4_1 (Pmod0 - 8) to pin P43_0 (Pmod0 - 7)

  • Build command: west build -p always -b rzg2lc_smarc/r9a07g044c22gbg/cm33 tests/drivers/gpio/gpio_basic_api