Demonstrates Vivado IP Catalog, Clocking Wizard and instantiation of the Xilinx MMCM PRIMITIVE. First part of the guide shows how to use the IP with the clocking wizard added into the Vivado project. For situations where there is just a one-time need to setup an MMCM template for a certain configuration of clock reference then the second part of the guide shows how to generate the parameterized MMCM instance in a separate project and then import only the generated VHDL module without adding the clocking wizard to the final project.

References:

• Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)
• 7 Series FPGAs Clocking Resources User Guide (UG472)
• Clocking Wizard LogiCORE IP Product Guide (PG065)

Open the Clocking Wizard by selecting it from the IP Catalog.

(Optionally) uncheck “Show disabled ports”. (Optionally) change Component Name clk_wiz_0 to something else. On the Board tab, sys clock and reset are selected under the Board Interface column .

On the Output Clocks tab, under Output Freq, 25.0 Mhz is entered for use as the pixel clock for a VGA screen size of 800x600. On the Summary tab, the Mult Counter field is set to 9.125 and the Divider Value is 36.5 which provide a 25 Mhz clock from the 100 Mhz system clock.

After hitting OK on the Clocking Wizard dialog, hit Generate from the Generate Output Products setup confirmation.

In the Sources window, select IP Sources and then expand under clk_wiz_0. Expand Instantiation Template then open clk_wiz_0.vho to find the Component Declaration and Instantiation Template that should be copied into the project.

Create new RTL project with Basys3 constraints and board definition. It will be a temporary project for running the Clock Wizard.

In FLOW NAVIGATOR pane, open IP INTEGRATOR, Create Block Design.

Design name: The default design_1 can be changed to something more meaningful like mmcm Directory: (or Choose Location...) Specify source set: the default Design Sources seems fine

In the Diagram pane: Press the + button to add IP. Search 'clk' and choose Clocking Wizard.

In the Diagram pane, Designer Assistance available. Run Connection Automation Check clk_wiz_0. clk_in1 and reset should be populated in Select Board Part Interface. After clicking OK, clk_in1 and reset have external port connection.

After creating the new IP Block from the Clocking Wizard, the Block Design environment is active and the Diagram pane is opened up to the clk_wiz_0 block. Otherwise the Block Design is opened by selecting Open File from the properties menu.

In the Diagram double-click the Clocking Wizard component (or select Customize Block... from clk_wiz_0 in the menu). Proceed with clock settings as described in the section above.

Under the Design Sources Hierarchy, right-click on design_1 (design_1.bd) and select Generate Output Products from the menu. Under Synthesis Options, Out of context per IP (default).

The MMCM entity can be found in the generated file <project>/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_sim_netlist.vhdl.

entity mmcm_clk_wiz_0_0 is
  port (
    clk_out1 : out STD_LOGIC;
    reset : in STD_LOGIC;
    locked : out STD_LOGIC;
    clk_in1 : in STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of mmcm_clk_wiz_0_0 : entity is true;
end mmcm_clk_wiz_0_0;

After importing the sim_netlist.vhdl into a project the attribute NotValidForBitStream must be removed or commented to use it in a synthesized design.

architecture Behavioral of rtl_top is
    signal clk_25M : std_logic;
begin

    u_clk : entity work.mmcm_clk_wiz_0_0
    port map (
        clk_out1 => clk_25M,
        reset => reset,
        locked => open,
        clk_in1 => clk
    );

Simulation shows nearly 1us until the MMCM output clock is established. The output waveform period is 40 ns.

Other helpful sources of information:

• Some discussions on Digilent here and here
• Dr. R. James Duckworth ECE 574: Modeling and Synthesis of digital systems MMCM Tutorial
• FPGA-Design-Flow-using-Vivado