T80 Port IO - red-bote/VHDL_Demos GitHub Wiki
Demonstrates Z80 output port with simulation result shown in timing diagram below.
org 0
di ; f3
ld sp, l_stack_top ; 31 00 84
ld a, 0xab ; 3e ab
out (0xc0), a ; d3 c0 0106
ld a, 0xcd ; 3e cd
out (0xc1), a ; d3 c1
jp l_entry ; c3 00 01
Execution of out opcode:
- $C0 is placed on the bottom half (A0 through A7) of the address bus
- the contents of Register A ($AB) also appear on the top half (A8 through A15) of the address bus at this time (i.e. ABC0)
- the byte contained in A ($AB) is placed on the data bus (DO)
The overall timing consists of 3 M-cycles, 11 T-states (4, 3, 4) (T-state #1 in M-state #3 lengthened to 2 clock cycles)
The T80 timing is not quite the same as an actual Z80, but overall is compatible. There is some discussion here
In the code above the IO addresses are $C0 and $C1. Partial address decoding with A7, A6 and A0 and along with /IORQ provide the control signal to the CE port of each register. The 4-bit output of each register is combined to form the 8-bit word connected to the external output.
