BCD Counter - red-bote/VHDL_Demos GitHub Wiki
A decimal counter (binary coded decimal) that integrates a cascaded counter with a seven-segment display.
mc14511 is an example of a dedicated BCD−to−seven segment decoder/driver.
As shown in the RTL schematic above, the main components in the top-level design are the prescaler, the BCD counter, and the SSD.
Each BCD digit has a clock-enable input, and a carry output. The clock-enable input of each digit is connected to the carry-out of the preceding digit.
The 4-bit outputs of the individual digits are concatenated into a 16-bit standard logic vector to be passed off to the SSD.
The individual digits are built around an instance of counters_5 imported from Xilinx XST User Guide examples. The register cnt_q0 synchronizes the logic to the CLR signal that resets the digit when it reaches a count of 10. The output Q is also handed off to a comparator that sets the carry signal when the count rolls over from 9 to 0.
