RDK‐E Bring‐Up Overview - rdkcentral/rdk-halif-aidl GitHub Wiki

This page provides a management-level view of the RDK-E bring-up process. It explains how HAL interfaces, vComponents, and Validation Test Suites (VTS) are developed, tested, and validated across multiple silicon vendors before being frozen at ABI V1.

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Key Principles

• Parallel component lifecycle: Each HAL component (e.g. Audio, Video, Tuner, Connectivity) progresses independently through the same lifecycle.

• Feedback-driven development: HAL specifications, vComponents, and VTS evolve together through iterative feedback loops.

• Two-silicon hard gate: A HAL component is frozen at ABI V1 only after all tests pass on the vDevice and the implementation has been validated on two silicon partners.

• Versioning discipline:

  • All repositories use git flow with SemVer.
  • Interfaces remain 0.xx.xx until frozen at ABI V1.
  • After ABI V1, only backward-compatible changes are permitted.
  • Directory structure + SemVer major versioning ensures VTS and HAL remain aligned.

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Portfolio Overview

The flow below represents the lifecycle for one HAL component. This same flow runs independently for each HAL component in parallel.

flowchart TD
    H1[Define high level requirements] --> H2[HAL AIDL and Doxygen]
    H2 --> H3[Detailed module specification]
    H3 --> H4[Feedback and refinement]
    H4 --> V1[vComponent bring up in vDevice]
    H4 --> T1[Create VTS from specification]
    V1 --> T2[Validate VTS versus vComponent levels L1 to L3]
    T1 --> T2 --> T3[Hardware and architecture validation level L4]
    T3 --> S1[Silicon bring up Vendor 1]
    S1 --> S2[Silicon bring up Vendor 2]
    S2 --> G[Hard gate all tests pass on vDevice and two silicon partners validated]
    G --> V2[ABI freeze and version V1]

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Swimlane View (Detailed Lifecycle for One Component)

This diagram shows the four parallel tracks for a single HAL component:

• HAL Specification
• vComponent Implementation
• VTS Development and Validation
• Silicon Partner Bring-Up

flowchart TD
    %% Lanes
    subgraph HAL[HAL interface and specification]
        H1[Define high level requirements]
        H2[HAL AIDL and Doxygen]
        H3[Detailed module specification]
        H4[Feedback and refinement]
        H6[ABI freeze and version V1]
    end

    subgraph VC[vComponent implementation]
        V1[vComponent bring up in vDevice]
        V2[Integration and iteration]
    end

    subgraph VTS[Testing and VTS]
        T1[Create VTS from specification]
        T2[Validate VTS versus vComponent levels L1 to L3]
        T3[Hardware and architecture validation level L4]
    end

    subgraph SIL[Silicon vendors]
        S1[Bring up Vendor 1]
        S2[Bring up Vendor 2]
        G[Hard gate all tests pass on vDevice and validated on two silicon partners]
    end

    %% Main flow
    H1 --> H2 --> H3 --> H4
    H4 --> V1
    H4 --> T1
    V1 --> V2 --> T2
    T1 --> T2 --> T3
    T3 --> S1 --> S2 --> G --> H6

    %% Feedback loops to refinement
    T2 --> H4
    V2 --> H4
    T3 --> H4
    S1 --> H4
    S2 --> H4