UNIVAC_418 - peregrineshahin/ChessProgrammingWiki GitHub Wiki
title: UNIVAC 418
a transistorized, 18-bit mainframe computer system by Sperry UNIVAC, first delivered as UNIVAC 418-I in June 1963, available with 4 to 16 KiWords of core memory with 4 μs cycle time, also available as militarized version UNIVAC 1218. The 418-II in November 1964 with up to 64 KiWords cut the cycle time to 2 μs and the 418-III came in 1969 with up to 128 KiWords further reduced to 750 ns memory cycles [2]. The 418 used ones' complement integer arithmetic with single or double precision (36-bit) operands. The 36-bit accumulator (A) was therefor divided by two upper and lower 18-bit AU and AL registers. A 3-bit index control register (ICR) controls the storing and loading of one flip-flop type B-register to and from eight main memory locations reserved as index registers (IR). Further, a 6-bit special register is a memory base register for some instructions, completed by the 17-bit instruction address register (IAR). All registers were displayed as binaries on the front panel in realtime with the ability to enter new values via buttons in a special mode. The UNIVAC 418-III had optional 36-bit floating-point support (1:8:27) and optional binary/decimal conversion instructions [3].
See also
Manuals
External Links
References
- ↑ UNIVAC 418 at OTC, Paddington, New South Wales, Image from Univac 418 – Paddington | Ex-OTC by Robert Brand, December 6, 2015
- ↑ UNIVAC 418 from Wikipedia
- ↑ UNIVAC 418-III System Description 1969 (pdf hosted by bitsavers.org)