ARM2 - peregrineshahin/ChessProgrammingWiki GitHub Wiki

title: ARM2

ARM2, (ARM3)

the Acorn RISC Machine ARMv2 architecture is a 32-bit CMOS reduced instruction set computer, first released in 1987 [1] as successor of the initial ARM (1985), designed by Sophie Wilson and Steve Furber in 1984. It features a 32-bit data bus, a 26-bit address space and sixteen 32-bit registers (r0 - r15, including PC and SP) [2], and a 3-stage pipelined (Fetch, Decode, Execute) Von Neumann architecture. The ARM is a bi endian machine, per default little-endian.

The ARM instruction set features three operand instructions, and conditional execution to avoid conditional branches. Some sample ARM assembly [3] :


  CMP    r0, r1           ; set flags
  ADDGE  r2, r2, r3       ; if (r0 >= r1) then r2 := r2 + r3;
  ADDLT  r2, r2, r4       ; else r2 := r2 + r4;

A 32-bit barrel shifter can be used without performance penalty with most arithmetic instructions and address calculations:


  ADD  r2, r3, r3, lsl #2 ; r2 := r3 + (r3 << 2)
                          ; → r2 := r3 + r3 * 4
                          ; → r2 := r3 * 5

The ARM2 processor was embedded inside the TASC ChessMachine plugged in as ISA card inside an IBM PC, running Gideon and The King [4], and was further used in various dedicated chess computers by Hegener & Glaser such as the Mephisto RISC.