Memory Map - pce-devel/huc GitHub Wiki

The 2MB physical address space available to the HuC6280 contains all of the memory-mapped I/O necessary to interface with the other chips, the CD subsystem, and the user (through the HuCard and joystick ports). Below is the full memory map for the TurboGrafx / PC Engine family. Each segment is labeled with its corresponding MPR register value ($00 - $FF), a description of the segment's use, its physical address location, and a "chip enable signal" or other descriptive text. The Develo Book describes the chip enable signal as an external signal that becomes true when that area of memory is accessed. Currently, it is not known if these signals correspond with any pins or traces available on the system motherboard. Signals in parentheses, such as ([o]CEP[/o]), represent chip enable signals that are internal to the HuC6280. The notation [o]SIGNAME[/o] is equivalent to a negative logic signal; that is, the signal is active when it is low instead of high.

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Physical Addresses	Segment : Address	Description	Chip enable signal
1FF400 - 1FF7FF	FF:1400 - FF:17FF	Interrupt controller	[o]CECG[/o] (internal)
1FF000 - 1FF3FF	FF:1000 - FF:13FF	8-bit I/O port	[o]CEIO[/o] (internal)
1FE800 - 1FEBFF	FF:0800 - FF:0BFF	PSG registers	[o]CEP[/o] (internal)
1FE400 - 1FE7FF	FF:0400 - FF:07FF	VCE registers	[o]CEK[/o]
1FE000 - 1FE3FF	FF:0000 - FF:03FF	VDC registers	[o]CE7[/o] (HuC6280 pin 60)
1F0000 - 1F7FFF	F8:0000 - FB:1FFF	Work RAM (8K, mirrored four times)	[o]CER[/o] (HuC6280 pin 61)
000000 - 0FFFFF	00:0000 - 7F:1FFF	HuCard/TurboChip ROM	ROM [o]CE[/o] (A20)

Physical Addresses	Segment : Address	Description	Chip enable signal
1FE020 - 1FE3FF	FF:0020 - FF:03FF	Copy of 32-byte register block (mirrored repeatedly)	[o]CE7[/o] (HuC6280 pin 60)
1FE018 - 1FE01F	FF:0018 - FF:001F	(Unused)	[o]CE7[/o] (HuC6280 pin 60)
1FE010 - 1FE017	FF:0010 - FF:0017	VDC #2 registers	[o]CE7[/o] (HuC6280 pin 60)
1FE008 - 1FE00F	FF:0008 - FF:000F	VPC registers	[o]CE7[/o] (HuC6280 pin 60)
1FE000 - 1FE007	FF:0000 - FF:0007	VDC #1 registers	[o]CE7[/o] (HuC6280 pin 60)
1F0000 - 1F7FFF	F8:0000 - FB:1FFF	Work RAM (32K)	[o]CER[/o] (HuC6280 pin 61)

Physical Addresses	Segment : Address	Description	Chip enable signal
1FE800 - 1FF80F	FF:0800 - FF:180F	CD-ROM / ASIC registers	[o]CEP[/o] (internal)
1EE000 - 1EE7FF	F7:0000 - F7:07FF	Back-up RAM (2K)	[o]CER[/o] (HuC6280 pin 61)
100000 - 10FFFF	80:0000 - 87:1FFF	Work RAM (64K)	[o]CER[/o] (HuC6280 pin 61)

Physical Addresses	Segment : Address	Description	Chip enable signal
1FE800 - 1FF80F	FF:0800 - FF:180F	ASIC registers (only relating to back-up RAM control)	[o]CEP[/o] (internal)
1EE000 - 1EE7FF	F7:0000 - F7:07FF	Back-up RAM (2K)	[o]CER[/o] (HuC6280 pin 61)

Physical Addresses	Segment : Address	Description	Chip enable signal
1FE800 - 1FFBFF	FF:0800 - FF:1BFF	CD-ROM / ASIC registers	[o]CEP[/o] (internal)
1EE000 - 1EE7FF	F7:0000 - F7:07FF	Back-up RAM (2K)	[o]CER[/o] (HuC6280 pin 61)
100000 - 10FFFF	80:0000 - 87:1FFF	Work RAM (64K)	[o]CER[/o] (HuC6280 pin 61)
0D0000 - 0FFFFF	68:0000 - 7F:1FFF	Work RAM (192K)	ROM [o]CE[/o] (A20)
000000 - 07FFFF	00:0000 - 3F:1FFF	BIOS ROM (512K)	ROM [o]CE[/o] (A20)

Physical Addresses	Segment : Address	Description	Chip enable signal
000000 - 03FFFF	00:0000 - 1F:1FFF	BIOS ROM (256K)	ROM [o]CE[/o] (A20)

Physical Addresses	Segment : Address	Description	Chip enable signal
1FF800 - 1FF9FF	FF:1800 - FF:19FF	ID locations	[o]CECG[/o] (internal)
0D0000 - 0FFFFF	68:0000 - 7F:1FFF	Work RAM (192K)	ROM [o]CE[/o] (A20)
000000 - 07FFFF	00:0000 - 3F:1FFF	BIOS ROM (512K)	ROM [o]CE[/o] (A20)

Physical Addresses	Segment : Address	Description	Chip enable signal
1FFA00 - 1FFBFF	FF:1A00 - FF:1BFF	Arcade Card I/O ports	[o]CECG[/o] (internal)
1FF800 - 1FF9FF	FF:1800 - FF:19FF	ID locations	[o]CECG[/o] (internal)
080000 - 087FFF	40:0000 - 43:1FFF	Arcade Card I/O pages	ROM [o]CE[/o] (A20)

Physical Addresses	Segment : Address	Description	Chip enable signal
1FFA00 - 1FFBFF	FF:1A00 - FF:1BFF	Arcade Card I/O ports	[o]CECG[/o] (internal)
1FF800 - 1FF9FF	FF:1800 - FF:19FF	ID locations	[o]CECG[/o] (internal)
0D0000 - 0FFFFF	68:0000 - 7F:1FFF	Work RAM (192K)	ROM [o]CE[/o] (A20)
080000 - 087FFF	40:0000 - 43:1FFF	Arcade Card I/O pages	ROM [o]CE[/o] (A20)
000000 - 07FFFF	00:0000 - 3F:1FFF	BIOS ROM (512K)	ROM [o]CE[/o] (A20)

Physical Addresses	Segment : Address	Description	Chip enable signal
080000 - 0FFFFF	40:0000 - 7F:1FFF	Mask ROM #2 (can be 128K, 256K)	ROM [o]CE[/o] (A20)
000000 - 07FFFF	00:0000 - 3F:1FFF	Mask ROM #1 (can be 128K, 256K)	ROM [o]CE[/o] (A20)

Physical Addresses	Segment : Address	Description	Chip enable signal
000000 - 0FFFFF	00:0000 - 7F:1FFF	Mask ROM (can be 128K, 256K, 512K)	ROM [o]CE[/o] (A20)

Physical Addresses	Segment : Address	Description	Chip enable signal
080000 - 0FFFFF	40:0000 - 7F:1FFF	ROM bank (512K of 2MB)	ROM [o]CE[/o] (A20)
000000 - 07FFFF	00:0000 - 3F:1FFF	ROM (512K, fixed)	ROM [o]CE[/o] (A20)
001FF0 - 001FF3	00:1FF0 - 00:1FF3	Bank select registers (write to 1FFx to map ROM bank #x to to the bank area)	ROM [o]CE[/o] (A20)

Physical Addresses	Segment : Address	Description	Chip enable signal
?????? - ??????	??:???? - ??:????	Battery-backed RAM
000000 - 0FFFFF	00:0000 - 7F:1FFF	Game ROM (256K)	ROM [o]CE[/o] (A20)