PCIe interface - patjak/facetimehd GitHub Wiki
PCIe registers
These registers sits on PCI Bar 0 and is related to the PCIe to S2 SoC interface (probably from Broadcom). They relate to PLL settings and power/link states.
0:0xd000
Possibly used to set the PCIe link state.
- Written values: 0x10 (L1 state?)
0:0xd120
- Written values: 0x1804
0:0xd124
Possibly information on PLL power state.
- Written values: 0xac5800
- Compared values: 0xac5800
0:0xd128
- Written values: 0x1f08, 0x1608, 0x1708
0:0xd12c
- Written values: 0x800005bf, 0x80008610, 0x8000fc00
Logic
- Put PCIe link into L1 state
- Turn off PLL
- Check if PLL actually turned off (fail if not)
- Do initialization sequence on 0xd128 and 0x12c