2026.01.22 Meeting Notes - parthenon-hpc-lab/parthenon GitHub Wiki
- Individual/group updates
- CAAR https://www.olcf.ornl.gov/caar/discovery-caar/
- bitwise identical sims/AMR segfaults
- Review non-WIP PRs
LR
- MG gid (so that internal coarse blocks also get an id)
- previously gid were dense, now not any more as to include level offset
- splitting comm buffers in sets
CAAR
- solvers would be relevant
- linking to trilinos?
- would benefit rad diffusion (FLD) in riot
- mixed precision in preconditioner?
- linear solves per cell
- use tensor cores?
- might be fine for smoothening
- or local linear solves for initial cycles
- block local timestepping
- yes, interesting
- for deep AMR hierarchies
- load balancing
- probably good combination with block local timestepping and solvers
- (parallel in time integration)
Bitwise identical sims/AMR issues
- follow up from last week: issue persists (in athenaPK)
- discovered that enabling sparse machinery (off by default) make the issue go away
- unclear if its' race condition or lib issue
- PG will provide reproducer
JM will schedule next sync tentatively on 19 Feb