2025.08.14 Meeting Notes - parthenon-hpc-lab/parthenon GitHub Wiki

• Individual/group updates
• Review non-WIP PRs

LR

• added some small fixes/updated existing PRs
• wants to get coalesced buffer comm in

AR

• added PR to fix imports for phdf python package
• will add install test to CI
• logic in phdf_diff returned true for nan. Will fix.
• (JM will add another feature, separately, for intermediate verbosity level: False <-> wrong variable <-> wrong cells)

PM

• fixed bug to fire up sim with more ranks than blocks at the root level

JMM

• went further down the asymmetry rabbit hole
• added some QOL improvements and bug fixes
  • fixed forceremesh metadata for flux vars
  • generate output before remesh (for debugging)
  • python plot improvements like bounds, colorbars, ...

JD

• got paperwork started to open source Riot

PG

• fixed a couple of downstream backward compatibility issues that resulted from recent changes in Parthenon #1297
  • last/next outputs
  • restart with new Restart variables
• discovered performance degradation over time (simple uniform grid runs over several minutes) on Nvidia GPUs
  • https://github.com/parthenon-hpc-lab/parthenon/issues/1304
  • PG will try to restart long running sim (to see if it's code or infrastructure)
  • FG will investigate, too
• working on downstream performance and memory optimization (for hero run on JUPITER)
  • separated flux kernels
    • now tight loops and no TeamPolicy
    • even reducing HBM access by 4x didn't increase performance
    • will share kernels with FG to investigate further
  • using coarse variables as reconstruction/flux buffers for tiled block loops
  • using LR's index split for comms is a big win
• added support for coarse outputs to openpmd

PRs

• asym tweaks https://github.com/parthenon-hpc-lab/parthenon/pull/1305 PM will review
  • want to keep output before remesh capability
• https://github.com/parthenon-hpc-lab/parthenon/pull/1297 AR will fix mentioned bug and then merge
• https://github.com/parthenon-hpc-lab/parthenon/pull/1292 LR changelog, PG final review tomorrow and merge
• IMEX example: https://github.com/parthenon-hpc-lab/parthenon/pull/1306/ should eventually be somewhere in (or around) Parthenon as an instructive example
• non-cart solver fix https://github.com/parthenon-hpc-lab/parthenon/pull/1244 LR will fix 3D index typo and merge
• https://github.com/parthenon-hpc-lab/parthenon/pull/1292
  • LR will add changelog. PG will review and merge
• TC timeout: https://github.com/parthenon-hpc-lab/parthenon/pull/1244
  • default value should be able to be set by downstream codes: done
  • set default to 5 min (so that if it breaks it break early)
  • PG review tomorrow and merge
• https://github.com/parthenon-hpc-lab/parthenon/pull/1142
  • kernel tuning is finicky anyway
  • this is a win, PG will merge
• buffer index split https://github.com/parthenon-hpc-lab/parthenon/pull/1271
  • PG will update input parameter logic as discussed in PR and then merge
• coalesced buffer: github.com/parthenon-hpc-lab/parthenon/pull/1192 off by default, merge now

Tentative next meeting 28 Aug