rcore on labeled rv

people

• th: xy,cy,wrj,dzy,zqy
• ict: byg,yzh,whz

content

educaition on step FPGA

• step FPGA: http://www.stepfpga.com
  • like a USB, simple, cheap, easy, follow by yourself
• build FPGA on Cloud
  • simple, no money, easy
• byg: we should consider the powerful debug function for os/arch design
• could be used on compiler, os, arch CPU design

demo of labeled rv from whz

• https://github.com/LvNA-system/labeled-RISC-V
• 4 个 kernel VM 绑定到 4 个 core 上, 独占一块物理内存: redis, md5, find, wordcount
• 一个 ARM 动态配置 cache 和 mem bw.

rcore talk from wrj

• https://github.com/oscourse-tsinghua/rcore_plus
• why choose rust to dev os
• how to design os using rust

rcore on labeled cpu

cy: Resource ownership on demand...?

• For now unmanaged sharing of resources (mem/bus bw, llc) causes problems.
• Online tuning of resource sharing, convey application requirements to underlying hw.
• High level target: re-investigate better language / architectural support for OS?

byg: idea highly similar to that of SDN

• application talk to underlying network.
• A outstanding difficulty of network optimization:
• the network engineer does not know what requirements the application wants to optimize.
• Thus communication is necessary.

next step

byg:

• 提供稳定的 SMP labeled RISC-V
• ...

cy:

• 将 rcore 跑到 RISC-V 上
• 在 rcore 中加入 control plane 的支持, 达到 20190124 whz 的演示水平
• 继续研究如何实现 cy 的想法 "让应用知道的高层语义, 一层一层通过类似 label 的机制传到硬件"

其他想法

• 现在 labeled 只演示了 VM, 能否做到 proc 层级?
• Use labeling mechanism not only for isolation but also for sharing.
• Finer grained control than cgroup?
• byg / xy: Deterministic execution, cycle level scheduling.
• byg / xy: take advantage of Rust's modularity: load kernel parts on demand (from the application).