Introduction - ntwong0/verilog-spi GitHub Wiki
verilog-spi
is a Verilog implementation of a SPI master module.
Port definitions:
module flex_spi(
// SPI-specific ports. This device is SPI master
output reg ss, // Optional, if not already provided by GPIO.
output reg sck, // Serial Clock
output wire mosi, // Master Out Slave In
input wire miso, // Master In Slave Out
// clocking and control from CPU
input wire clk, // System clock, can be fed by clock divider instead
// functionality
input wire rst, // Resets the SPI module
input wire en, // If true, SPI I/F should proceed to TRANSFER
input wire oe, // If true, SPI I/F should output from rx_packet to data
input wire we, // If true, write from data to tx_packet
input wire cpol, // SPI Clock Polarity
input wire cpha, // SPI Clock Phase
input wire [ 3:0] xfer_len, // Determines bit length of the SPI transaction
// status to CPU
output wire busy, // Indicates a SPI transaction is in progress
output wire done, // Indicates a SPI transaction has completed
// data I/O with CPU
inout wire [15:0] data // Data in/out from/to microcontroller
);