Running CPU86 on max1000 board

Some information on the Arrow's max1000 FPGA board.

It's a nice, yet cheap board at ~$30, sporting a powerful Intel® MAX® 10 FPGA.

It has been covered in a nice post on Hackaday, which inspired me buying one board, and trying to port CPU86

Challenges

• like the PapilioOne, small FPGA and only about 48kB internal BlockRam
• unlike the PapilioDuo, no onboard external SSRAM
• interestingly, the max1000 sports a beefy 8MB SDRAM

(ab)Using SDRAM, for fun and profit..

How do you run a CPU that expects 640kB of static RAM, on a (small) FPGA that only offers about 48kB internal blockram and some big SDRAM chip ?

You then decide to (ab)use the dynamic RAM as a static RAM, of course !

The main issue being that the CPU86 core is not designed to interface with a dynamic RAM, because memory accesses must be synchronous to the CPU clock (no wait states or such)

The idea is to use the FPGA vendor SDRAM controller IP (small, fast, debugged), and clock both the SDRAM and controller to a clock way faster than the CPU, such that it appears to be synchronous (like a static RAM)

By trial and errors, I noticed that reasonable SDRAM memory accesses require more than 16 cycles, and less than 20 cycles

As I plan to run CPU86 at 5MHz (original PC clock was 4.77MHz), it means clocking SDRAM+controller at 100MHz

I actually tried that settings, and it just worked fine !

Ok, I admit it may be seen as an overkill to use a 2018 ~$30 FPGA board with 8MB@100MHz SDRAM to implement a 640kB RAM system @5MHz from the 1980s that cost about $1000 or more at that time; but, still.. :-)