2019 - June 14

Present: thosou & denlar

Hashtags (topics)

• Sw cap toolbox
• State space
• Automated state space generation
• Interleaving and multi-phase
• Simulator, AC, tran
• Topology synthesis
• Schematic output
• Controller design
• Switch conductance modulation (digital and analog)
• Verilog-A/AMS output
• Netlist (cadence schematic)
• Topology (automated generation)
• Closed loop optimization
• Switched cap sizing for multi-topology
• Gate driver

Converter use cases

• Step-up converter for energy harvester
  • Low input voltage
  • High step-up ratio
  • External capacitors
  • Multi-topology
• Microprocessor
  • Vin = 1.8 V
  • Vout = 0.6-1.0 V
  • Iout = 1-100 mA
  • Internal capacitors
  • Multi-topology
• High-voltage ladder step-down
  • Vin = 100 V
  • Vout = 12 V
  • Iout = 0.5 A
  • External capacitors
  • Single-topology
• Li-Ion step-down
  • Vin = 3.0-4.5 V
  • Vout = 1.2 V
  • Iout = 1-100 mA
  • External capacitors
  • Multi-topology
• Zn-Air step-up
  • Vin = 0.9 - 1.8V
  • External capacitors
  • Single-topology
• High-power step-down
  • Vin = 24V
  • Vout = 12V
  • Electrolytic capacitors
  • Single-topology

Targeted system

• Switch-cap
• DC-DC
• PLL/DLL
• Delta-sigma

Circuit design

• Verilog-A/AMS model
• Pspice
• LTspice
• Cadence