Simulating (part of) an ASIC with spice-noqsi and ngspice

The project here is a pulse height discriminator using Open-IP along with a custom comparator circuit. I've organized it in three directories:

• Schematic for the board schematics
• Symbols for custom symbols
• Simulation for test fixtures and models

Schematics

The Schematic directory has the schematic of the discriminator subcircuit:

The discriminator has inputs:

• IN (analog) is the signal input.
• LL (analog) is the lower voltage level, above which the discriminator will trigger.
• HL (analog) is the upper voltage level.
• CLK (digital) is the clock that sychronizes the output pulses with the external system.

Outputs:

• LLP is a digital pulse that indicates that an analog pulse on IN rose above LL but not above HL.
• HLP is a digital pulse that indicates that an analog pulse on IN rose above HL.

Output pulses rise following the first rising edge of CLK after IN falls below LL and fall on the following rising edge of CLK. X1 and X5 compare IN with LL and HL respectively. Latches X2 and X6 asychronously capture the comparator outputs. Flip-flops X3 and X9 synchronize the outputs to the clock. X9 inhibits this if IN is above LL. X13 supresses the LLP pulse if the high level latch, X6 is set. X14 resets both latches when an outout pulse is generated.

X10 provides voltage bias to the controlled current sources in the comparators (standard Open-IP practice). To minimize interactions between circuit blocks, it is common Open-IP practice to buffer digital signals that fan out internally. X11 and X12 buffer CLK while X4 and X8 buffer the outputs.

And here's the schematic of the comparator subcircuit:

The comparator has three differential gain stages, powered by the analog rails Vss and Vdd, followed by a logic buffer powered by the digital rails, Vss1 and Vdd1.

Each of the subcircuit schematics includes its corresponding symbol with a graphical=1 attribute attached, but with nothing attached to their pins. This is not necessary (gnetlist completely ignores such symbols), but it is helpful to people reading the schematic.

These schematics use special symbols, specific to SPICE circuits, to implement hierarchy. A spice-subcircuit-LL symbol names the subcircuit. spice-subcircuit-IO symbols identify the inputs and outputs. The numeric part of their refdes attributes must match the pinseq attributes of the corresponding pins of the symbol for the subcircuit. Stuart Brorson's tutorial gives more details of this approach, and these schematics are compatible with the spice-sdb back end as well as the spice-noqsi one. They are not compatible with printed circuit back ends, but this is an ASIC project, so that doesn't matter.

The Schematic directory has a suitable gafrc file, telling the tools where custom symbols and subcircuit source files are:

(source-library ".")
(component-library "../Symbols")

There is no Makefile in the schematic directory: this is only a fragment of a project.

Simulation

This project handles hierarchy in SPICE rather than gnetlist. Gnetlist cannot traverse a hierarchy defined by SPICE-specfic symbols. Thus, in the Simulation directory, there is a gnetlistrc file containing the line (hierarchy-traversal "disabled").

Here's the simulation "test fixture":

For this project, no spice-prototype attributes are required: the defaults suffice.

There is, of course, a Makefile for simulation:

GNET=gnetlist -L ../../.. -g spice-noqsi
#
# Alternate for using the spice-sdb back end instead
# GNET=gnetlist -g spice-sdb
SPICE=ngspice

IMPORTS=DISCRI.sch Comparator.sch
CIRCUITS=DISCRI.cir Comparator.cir DISCRItest.cir
MODELS=../Models/submicron.inc ../Models/openIP.inc

%.cir : %.sch
	$(GNET) $< -o $@

.PHONY : simulation

simulation : $(CIRCUITS) control.cir
	$(SPICE) $(CIRCUITS) control.cir $(MODELS) 

DISCRI.sch : ../Schematic/DISCRI.sch
	cp $< $@

Comparator.sch : ../Schematic/Comparator.sch
	cp $< $@

clean : 
	rm -f $(IMPORTS) $(CIRCUITS) \#* *~

This makes a copies of DISCRI.sch and Comparator.sch in the Simulation directory. I like this approach because I often find myself tinkering with simulation schematics. Since I didn't use the file= mechanism, I explicitly list all input files in the SPICE command line.

Typing make plots the response of the circuit to three input pulses of different heights. There is a brief transient at the start due to the lack of any flip-flop initialization. This might be expected in a real circuit as well.

More Resources

Here's where to get more Open-IP symbols for schematics.

These BSIM model parameters are more realistic than the level 6 parameters in submicron.inc I used here, but simulations using them are about three times slower. Of course, if you intend to fabricate chips, you should use your foundry's proprietary parameter sets for better accuracy.