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Welcome to the gnet-spice-noqsi wiki!
This code is a netlist "back end" for producing SPICE simulation code from gEDA schematics. It gives the user more control of the process than previous SPICE back ends. This allows you to use gEDA's native hierarchy approach to create hierarchical netlists and subcircuit libraries, rather than special SPICE-oriented symbols. It also provides for customization of the netlist generation via spice-prototype attributes. This helps avoid the conflicts that overloaded attributes like pinseq and value cause between SPICE and printed circuit layout: you can now create schematics that can drive both simulation and layout without modification.
To get started, have a look at a simple circuit:
A more complicated design, suitable both for simulation and layout:
You can also use this for IC design:
Finally, the Reference Document