PJIT Monitor (pmon) - nonarkitten/pseudo-jit GitHub Wiki
To examine any memory location, simply enter the address in hexadecimal. Only hexadecimal input is supported. PMON can take 8, 16, 24 and 32-bit addresses as input and will zero-extend addresses short of 24-bit. All basic operations to and from memory are done in WORDS or 16-bit whole values.
] FC0000 FC0000: 1111
To display a block of memory we simply prefix the address with a period.
] .FC0010 FC0002: 4EF9 00FC 00D2 0000 FFFF 0022 0005 0022
We can combine these to show memory from the first address to the second.
] FC0000.FC0010 FC0000: 1111 4EF9 00FC 00D2 0000 FFFF 0022 0005 0022
We can also specify multiple addresses separated by a space.
] FC0000 FC0008 FC0000: 1111 FC0008: 0000
To affect a write to the address, we can add a colon.
] DFF180: 0FFF
After the colon we can provide as many words as we like to be written to consecutive words in memory.
] DFF180: 0FFF 0F0F 0FF0
When writing or reading, it is important to only do with EVEN memory addresses. Attempting to access ODD memory locations will be ignored. Pmon provides very little in terms of error reporting, it's up to the user to understand why things didn't work.
] FC0018S FC0018: "exec 33.192 (8 Oct 1986)\r\n"
The S letter will parse memory from the last address as a string and output that. Only the first 256 characters will be displayed for very long strings.
The R letter is the "run" command and will reset and restart PJIT from that memory address. PJIT will run CONCURRENTLY to pmon.
The B letter sets a breakpoint at the specified address. When the breakpoint is reached, PJIT will stop and dump the CPU state.
Prints the current CPU state. If PJIT is presently running, it will be momentarily paused to create 'snapshot' data.
Stops or pauses PJIT and dumps the CPU state.
Continues PJIT from the last address.
Performs a single PJIT instruction (step). In addition to showing the CPU state, PJIT will also emit the instruction executed.
Enable (T1) or disable (T0) trace. While trace is enabled, every instruction will be echoed to the console along with the CPU state. This will slow down PJIT. In 68020 mode you can also set trace to T2 which will only dump CPU state when a branch is encountered.
] P00 D0: 000000000
Shows the value of Processor register 00. This must only be a value from 00-1F. Note that in the response, Pmon will always use "real" register names for convinience. You can also use D0-D7 and A0-A7 after the P.
The registers are:
00-07 Data Registers D0 to D7 08-0F Address Registers A0 to A7 10 Source Function Code 11 User Stack Pointer 12 Destination Function Code 13 Vector Base Register, Status Register and Condition Code 14 Cache Control Register 15 Cache Address Register 16 MMU Translation Control Register 17 Master Stack Pointer 18 Instruction Transparent Translation Register 0 19 Interrupt Stack Pointer 1A Instruction Transparent Translation Register 1 1B MMU Status Register 1C Data Transparent Translation Register 0 1D User Root Pointer 1E Data Transparent Translation Register 1 1F Supervisor Root Pointer A0-A7 Alias for 08-0F D0-D7 Alias for 00-07
] PD0: 0000 D0: 000000000
Sets processor register 00 (D0) to 0000. Data regsters support 8-bit (bytes), 16-bit (word) and 32-bit (long word) values and will leave the unwritten bits alone. Address registers support word and long word writes and will sign-extend word writes. All other registers are 32-bit only.
Shows the value stored at EEPROM address. Addresses are from 000-FFF and only byte reads and writes are supported. The EEPROM is partitioned into sixteen pages of 256 bytes each. At boot, the CPU will scan for the latest, valid copy.