• Vector Signal Transceiver
  • Device Characteristics
    • NIRFSG_ATTR_FPGA_BITFILE_PATH
    • NIRFSG_ATTR_FPGA_TARGET_NAME
  • Events
    • NIRFSG_ATTR_EVENTS_DELAY
  • IQ Out Port
    • NIRFSG_ATTR_IQ_OUT_PORT_CARRIER_FREQUENCY
    • NIRFSG_ATTR_IQ_OUT_PORT_COMMON_MODE_OFFSET
    • NIRFSG_ATTR_IQ_OUT_PORT_LEVEL
    • NIRFSG_ATTR_IQ_OUT_PORT_LOAD_IMPEDANCE
    • NIRFSG_ATTR_IQ_OUT_PORT_OFFSET
    • NIRFSG_ATTR_IQ_OUT_PORT_TEMPERATURE
    • NIRFSG_ATTR_IQ_OUT_PORT_TERMINAL_CONFIGURATION
  • Signal Path
    • NIRFSG_ATTR_ABSOLUTE_DELAY
    • NIRFSG_ATTR_INTERPOLATION_DELAY
    • NIRFSG_ATTR_LO_FREQUENCY_STEP_SIZE
    • NIRFSG_ATTR_LO_VCO_FREQUENCY_STEP_SIZE
    • NIRFSG_ATTR_LO_PLL_FRACTIONAL_MODE_ENABLED
    • NIRFSG_ATTR_LO_SOURCE
    • NIRFSG_ATTR_OUTPUT_PORT
    • NIRFSG_ATTR_RELATIVE_DELAY
    • NIRFSG_ATTR_RF_BLANKING_SOURCE
    • NIRFSG_ATTR_SELECTED_PORTS
    • NIRFSG_ATTR_AVAILABLE_PORTS
  • Triggers
    • NIRFSG_ATTR_SYNC_SAMPLE_CLOCK_DIST_LINE
    • NIRFSG_ATTR_SYNC_SAMPLE_CLOCK_MASTER
    • NIRFSG_ATTR_SYNC_SCRIPT_TRIGGER_DIST_LINE
    • NIRFSG_ATTR_SYNC_SCRIPT_TRIGGER_MASTER
    • NIRFSG_ATTR_SYNC_START_TRIGGER_DIST_LINE
    • NIRFSG_ATTR_SYNC_START_TRIGGER_MASTER
  • Upconverter
    • NIRFSG_ATTR_UPCONVERTER_FREQUENCY_OFFSET

Data type	Access	Coercion	High Level Functions
ViString	RO	None	None

Returns a string containing the path to the location of the current NI-RFSG instrument driver FPGA extensions bitfile, a .lvbitx file, that is programmed on the device. You can specify the bitfile location using the Driver Setup string in the optionString parameter of the niRFSG_InitWithOptions function.

NI-RFSG instrument driver FPGA extensions enable you to use pre-compiled FPGA bitfiles to customize the behavior of the vector signal transceiver FPGA while maintaining the functionality of the NI-RFSG instrument driver.

Supported Devices: PXIe-5644/5645/5646, PXIe-5820/5830/5831/5832/5840/5841

Related Topics

NI-RFSG Instrument Driver FPGA Extensions

Driver Setup Options

Numeric Value	Data type	Access	Coercion	High Level Functions
1150251	ViString	RO	None	None

Returns a string that contains the name of the FPGA target being used. This name can be used with the RIO open session to open a reference to the FPGA.

This attribute is channel dependent if multiple FPGA targets are supported.

Supported Devices: PXIe-5820/5830/5831/5832/5840/5841

Numeric Value	Data type	Access	Coercion	High Level Functions
1150154	ViReal64	R/W	None	None

Specifies the delay, in seconds, applied to the Started Event, Done Event, and all Marker Events with respect to the analog output of the RF signal generator. To set this attribute, the NI-RFSG device must be in the Configuration or Generation state.

	Note   If you decrease the event delay during generation, some markers may be dropped.
By default, markers and events are delayed to align with the waveform data generated from the device. This attribute adds an additional delay to markers and events. Use this attribute to adjust the time delay between events and the corresponding data.

Units: Seconds

Valid Values:

PXIe-5644/5645: -1.217 μs to 67.050 μs

PXIe-5646: -0.896 μs to 64.640 μs

PXIe-5820/5830/5831/5832/5840/5841: 0 μs to 3.276 μs

Supported Devices: PXIe-5644/5645/5646, PXIe-5820/5830/5831/5832/5840/5841

Related Topics

Events

Numeric Value	Data type	Access	Coercion	High Level Functions
1150145	ViReal64	R/W	None	None

Specifies the frequency of the I/Q OUT port signal. The onboard signal processing (OSP) applies the specified frequency shift to the I/Q data before the data is sent to the digital-to-analog converter (DAC). To set this attribute, the NI-RFSG device must be in the Configuration state.

	Note For the PXIe-5820, NI recommends using the NIRFSG_ATTR_FREQUENCY attribute.

	Note  For the PXIe-5645, this attribute is ignored if you are using the RF ports.
Units: hertz (Hz)

Valid Values:

PXIe-5645: -60 MHz to 60 MHz

PXIe-5820: -500 MHz to 500 MHz

Supported Devices: PXIe-5645, PXIe-5820

Numeric Value	Data type	Access	Coercion	High Level Functions
1150148	ViReal64	R/W	None	None

Specifies the common-mode offset applied to the signals generated at each differential output terminal. This attribute applies only when you set the NIRFSG_ATTR_IQ_OUT_PORT_TERMINAL_CONFIGURATION attribute to NIRFSG_VAL_DIFFERENTIAL. Common-mode offset shifts both positive and negative terminals in the same direction.

To use this attribute, you must use the channelName parameter of the niRFSG_SetAttributeViReal64 function to specify the name of the channel you are configuring. For the PXIe-5645, you can configure the I and Q channels by using I or Q as the channel string, or set the channel string to "" (empty string) to configure both channels. For the PXIe-5820, the only valid value for the channel string is "" (empty string).

	Note  For the PXIe-5645, this attribute is ignored if you are using the RF ports.
To set this attribute, the NI-RFSG device must be in the Configuration state.

Units: Volts

Valid Values:

PXIe-5645: -0.8 V to 0.8 V if you set the NIRFSG_ATTR_IQ_OUT_PORT_LOAD_IMPEDANCE attribute to 50 Ω. The valid values are -1.2 V to 1.2 V if you set the NIRFSG_ATTR_IQ_OUT_PORT_LOAD_IMPEDANCE attribute to 100 Ω.

PXIe-5820: -0.25 V to 1.5 V

	Note  The valid range is dependent on the load impedance.
Supported Devices: PXIe-5645, PXIe-5820

Numeric Value	Data type	Access	Coercion	High Level Functions
1150147	ViReal64	R/W	None	None

Specifies the amplitude of the generated signal in volts, peak-to-peak (Vpk-pk). For example, if you set this attribute to 1.0, the output signal ranges from -0.5 volts to 0.5 volts.

To use this attribute, you must use the channelName parameter of the niRFSG_SetAttributeViReal64 function to specify the name of the channel you are configuring. For the PXIe-5645, you can configure the I and Q channels by using I or Q as the channel string, or set the channel string to "" (empty string) to configure both channels. For the PXIe-5820, the only valid value for the channel string is "" (empty string).

To set this attribute, the NI-RFSG device must be in the Configuration state.

	Note  For the PXIe-5645, this attribute is ignored if you are using the RF ports.
Refer to the specifications document for your device for allowable output levels.

Units: Volts, peak-to-peak (Vpk-pk)

Valid Values:

PXIe-5645: 1 Vpk-pk maximum if you set the NIRFSG_ATTR_IQ_OUT_PORT_TERMINAL_CONFIGURATION attribute to NIRFSG_VAL_DIFFERENTIAL, and 0.5 Vpk-pk maximum if you set the NIRFSG_ATTR_IQ_OUT_PORT_TERMINAL_CONFIGURATION attribute to NIRFSG_VAL_SINGLE_ENDED.

PXIe-5820: 3.4 Vpk-pk maximum for signal bandwidth less than 160 MHz, and 2 Vpk-pk maximum for signal bandwidth greater than 160 MHz.

	Note  The valid values are only applicable when you set the NIRFSG_ATTR_IQ_OUT_PORT_LOAD_IMPEDANCE attribute to 50 Ω and when you set the NIRFSG_ATTR_IQ_OUT_PORT_OFFSET attribute to 0.
Default Value: 0.5 volts

Supported Devices: PXIe-5645, PXIe-5820

Numeric Value	Data type	Access	Coercion	High Level Functions
1150163	ViReal64	R/W	None	None

Specifies the load impedance connected to the I/Q OUT port. To set this attribute, the NI-RFSG device must be in the Configuration state.

To use this attribute, you must use the channelName parameter of the niRFSG_SetAttributeViReal64 function to specify the name of the channel you are configuring. For the PXIe-5645, you can configure the I and Q channels by using I or Q as the channel string, or set the channel string to "" (empty string) to configure both channels. For the PXIe-5820, the only valid value for the channel string is "" (empty string).

	Note  For the PXIe-5645, this attribute is ignored if you are using the RF ports.
Units: Ohms

Valid Values: Any value greater than 0. Values greater than or equal to 1 megaohms (MΩ) are interpreted as high impedance.

Default Value: 50 Ω if you set the NIRFSG_ATTR_IQ_OUT_PORT_TERMINAL_CONFIGURATION attribute to NIRFSG_VAL_SINGLE_ENDED, and 100 Ω if you set the NIRFSG_ATTR_IQ_OUT_PORT_TERMINAL_CONFIGURATION attribute to NIRFSG_VAL_DIFFERENTIAL.

Supported Devices: PXIe-5645, PXIe-5820

Numeric Value	Data type	Access	Coercion	High Level Functions
1150149	ViReal64	R/W	None	None

Specifies the value, in volts, that the signal generator adds to the arbitrary waveform data. To set this attribute, the NI-RFSG device must be in the Configuration state.

To use this attribute, you must use the channelName parameter of the niRFSG_SetAttributeViReal64 function to specify the name of the channel you are configuring. For the PXIe-5645, you can configure the I and Q channels by using I or Q as the channel string, or set the channel string to "" (empty string) to configure both channels. For the PXIe-5820, the only valid value for the channel string is "" (empty string).

PXIe-5645: The waveform may be scaled in DSP prior to adding offset and the device state may be changed in order to accommodate the requested offset.

PXIe-5820: The waveform is not automatically scaled in DSP. To prevent DSP overflows, use the NIRFSG_ATTR_ARB_PRE_FILTER_GAIN attribute to scale the waveform to provide additional headroom for offsets.

	Note  For the PXIe-5645, this attribute is ignored if you are using the RF ports.
Units: Volts

Supported Devices: PXIe-5645, PXIe-5820

Numeric Value	Data type	Access	Coercion	High Level Functions
1150161	ViReal64	RO	None	None

Returns the temperature, in degrees Celsius, of the I/Q Out circuitry on the device.

	Note  If you query this attribute during RF list mode, list steps may take longer to complete during list execution.
Units: Degrees Celsius

Supported Devices: PXIe-5645, PXIe-5820

Numeric Value	Data type	Access	Coercion	High Level Functions
1150146	ViInt32	R/W	None	None

Specifies whether to use the I/Q OUT port for differential configuration or single-ended configuration. If you set this attribute to NIRFSG_VAL_SINGLE_ENDED, you must terminate the negative I and Q output connectors with a 50 Ohm termination.

If you set this attribute to NIRFSG_VAL_SINGLE_ENDED, the positive I and Q connectors generate the resulting waveform. If you set this attribute to NIRFSG_VAL_DIFFERENTIAL, both the positive and negative I and Q connectors generate the resulting waveform.

To use this attribute, you must use the channelName parameter of the niRFSG_SetAttributeViInt32 function to specify the name of the channel you are configuring. For the PXIe-5645, you can configure the I and Q channels by using I or Q as the channel string, or set the channel string to "" (empty string) to configure both channels. For the PXIe-5820, the only valid value for the channel string is "" (empty string).

	Note  For the PXIe-5645, this attribute is ignored if you are using the RF ports.
To set this attribute, the NI-RFSG device must be in the Configuration state.

Defined Values:

NIRFSG_VAL_DIFFERENTIAL	Sets the terminal configuration to differential.
NIRFSG_VAL_SINGLE_ENDED	Sets the terminal configuration to single-ended.
Default Value: NIRFSG_VAL_DIFFERENTIAL

PXIe-5820: The only valid value for this attribute is NIRFSG_VAL_DIFFERENTIAL.

Supported Devices: PXIe-5645, PXIe-5820

Related Topics

Differential and Single-Ended Operation (I/O Interface)

Numeric Value	Data type	Access	Coercion	High Level Functions
1150225	ViReal64	R/W	None	None

Specifies the sub-Sample Clock delay, in seconds, to apply to the I/Q waveform. Use this attribute to reduce the trigger jitter when synchronizing multiple devices with NI-TClk. This attribute can also help maintain synchronization repeatability by writing the absolute delay value of a previous measurement to the current session.

To set this attribute, the NI-RFSG device must be in the Configuration state.

	Note  If this attribute is set, NI-TClk cannot perform any sub-Sample Clock adjustment.

	Note  The resolution of this attribute is a function of the I/Q sample period at 15E(-6) times that sample period.
Units: Seconds

Valid Values: Plus or minus half of one Sample Clock period

Supported Devices: PXIe-5820/5840/5841

Numeric Value	Data type	Access	Coercion	High Level Functions
1150153	ViReal64	R/W	None	None

Specifies the delay, in seconds, to apply to the I/Q waveform. To set this attribute, the NI-RFSG device must be in the Configuration state.

Units: Seconds

Valid Values: Plus or minus half of one I/Q sample period

Supported Devices: PXIe-5644/5645/5646

Numeric Value	Data type	Access	Coercion	High Level Functions
1150151	ViReal64	R/W	None	None

Specifies the step size for tuning the local oscillator (LO) phase-locked loop (PLL).

When the NIRFSG_ATTR_LO_PLL_FRACTIONAL_MODE_ENABLED attribute is enabled, the specified step size affects the fractional spur performance of the device. When the NIRFSG_ATTR_LO_PLL_FRACTIONAL_MODE_ENABLED attribute is disabled, the specified step size affects the phase noise performance of the device.

The valid values for this attribute depend on the NIRFSG_ATTR_LO_PLL_FRACTIONAL_MODE_ENABLED attribute.

PXIe-5644/5645/5646—If you disable the NIRFSG_ATTR_LO_PLL_FRACTIONAL_MODE_ENABLED attribute, the specified value is coerced to the nearest valid value.

PXIe-5840/5841—If you disable the NIRFSG_ATTR_LO_PLL_FRACTIONAL_MODE_ENABLED attribute, the specified value is coerced to the nearest valid value that is less than or equal to the desired step size.

NIRFSG_ATTR_LO_PLL_FRACTIONAL_MODE_ENABLED Attribute Setting	NIRFSG_ATTR_LO_FREQUENCY_STEP_SIZE Attribute Valid Values on PXIe-5644/5645	NIRFSG_ATTR_LO_FREQUENCY_STEP_SIZE Attribute Valid Values on PXIe-5646	NIRFSG_ATTR_LO_FREQUENCY_STEP_SIZE Attribute Valid Values on PXIe-5840/5841	NIRFSG_ATTR_LO_FREQUENCY_STEP_SIZE Attribute Valid Values on PXIe-5830/5831/5832		NIRFSG_ATTR_LO_FREQUENCY_STEP_SIZE Attribute Valid Values on PXIe-5841 with PXIe-5655*
				LO1	LO2
NIRFSG_VAL_ENABLE	50 kHz to 24 MHz	50 kHz to 25 MHz	50 kHz to 100 MHz	8 Hz to 400 MHz	4 Hz to 400 MHz	1 nHz to 50 MHz
NIRFSG_VAL_DISABLE	4 MHz, 5 MHz, 6 MHz, 12 MHz, or 24 MHz	2 MHz, 5 MHz, 10 MHz, or 25 MHz	1 MHz, 5 MHz, 10 MHz, 25 MHz, 50 MHz, or 100 MHz	—	—
* Values up to 100 MHz are coerced to 50 MHz.
Units: hertz (Hz)

Default Values:

PXIe-5644/5645/5646: 200 kHz

PXIe-5830: 2 MHz

PXIe-5831/5832 (RF port): 8 MHz

PXIe-5831/5832 (IF port): 2 MHz, 4 MHz

PXIe-5840/5841:

• Fractional mode: 500 kHz
• Integer mode: 10 MHz for frequencies less than or equal to 4 GHz. 20 MHz for frequencies greater than 4 GHz.

PXIe-5841 with PXIe-5655: 500 kHz

Supported Devices: PXIe-5644/5645/5646, PXIe-5830/5831/5832/5840/5841

Numeric Value	Data type	Access	Coercion	High Level Functions
1150257	ViReal64	R/W	None	None

Specifies the step size for tuning the internal voltage-controlled oscillator (VCO) used to generate the LO signal.

Valid Values:

LO1: 1 Hz to 50 MHz

LO2: 1 Hz to 100 MHz

Default Value: 1 MHz

Supported Devices: PXIe-5830/5831/5832

Numeric Value	Data type	Access	Coercion	High Level Functions
1150152	ViInt32	R/W	None	None

Specifies whether to use fractional mode for the local oscillator (LO) phase-locked loop (PLL). This attribute enables or disables fractional frequency tuning in the LO. Fractional mode provides a finer frequency step resolution and allows smaller values for the NIRFSG_ATTR_LO_FREQUENCY_STEP_SIZE attribute. However, fractional mode may introduce non-harmonic spurs.

This attribute applies only if you set the NIRFSG_ATTR_LO_SOURCE attribute to NIRFSG_VAL_LO_SOURCE_ONBOARD_STR.

To use this attribute for the PXIe-5830/5831/5832, you must use the channelName parameter of the niRFSG_SetAttributeViInt32 function to specify the name of the channel you are configuring. You can configure the LO1 and LO2 channels by using lo1 or lo2 as the channel string, or set the channel string to lo1,lo2 to configure both channels. For all other devices, the the only valid value for the channel string is "" (empty string).

	Note  For the PXIe-5841 with PXIe-5655, this attribute is ignored if the PXIe-5655 is used as the LO source.
Defined Values:

NIRFSG_VAL_ENABLE	Enables fractional mode for the LO PLL.
NIRFSG_VAL_DISABLE	Disables fractional mode for the LO PLL.
Default Value: NIRFSG_VAL_ENABLE

Supported Devices: PXIe-5644/5645/5646, PXIe-5830/5831/5832/5840/5841

Related Topics

Refer to the local oscillators topic appropriate to your device for more information about using fractional mode.

Numeric Value	Data type	Access	Coercion	High Level Functions
1150150	ViString	R/W	None	None

Specifies whether to use the internal or external local oscillator (LO) source. If the NIRFSG_ATTR_LO_SOURCE attribute is set to "" (empty string), NI-RFSG uses the internal LO source. To set this attribute, the NI-RFSG device must be in the Configuration state.

To use this attribute for the PXIe-5830/5831/5832, you must use the channelName parameter of the niRFSG_SetAttributeViString function to specify the name of the channel you are configuring. You can configure the LO1 and LO2 channels by using lo1 or lo2 as the channel string, or set the channel string to lo1,lo2 to configure both channels. For all other devices, the the only valid value for the channel string is "" (empty string).

	Note For the PXIe-5841 with PXIe-5655, RF list mode is not supported when this attribute is set to NIRFSG_VAL_LO_SOURCE_SG_SA_SHARED_STR.
Defined Values:

NIRFSG_VAL_LO_SOURCE_ONBOARD_STR	Uses an internal LO as the LO source. If you specify an internal LO source, the LO is generated inside the device itself. **PXIe-5831/5832—**This configuration uses the onboard LO of the PXIe-3622, using the LO2 stage. **PXIe-5831/5832 with PXIe-5653—**This configuration uses the onboard LO of the PXIe-5653 when associated with the PXIe-3622. **PXIe-5841 with PXIe-5655—**This configuration uses the onboard LO of the PXIe-5655.
NIRFSG_VAL_LO_SOURCE_LO_IN_STR	Uses an external LO as the LO source. Connect a signal to the LO IN connector on the device and use the NIRFSG_ATTR_UPCONVERTER_CENTER_FREQUENCY attribute to specify the LO frequency.
NIRFSG_VAL_LO_SOURCE_SECONDARY_STR	Uses the PXIe-5831/5840 internal LO as the LO source. This value is valid only on the PXIe-5831 with PXIe-5653 and PXIe-5832 with PXIe-5653.
NIRFSG_VAL_LO_SOURCE_SG_SA_SHARED_STR	Uses the same internal LO during NI-RFSA and NI-RFSG sessions. NI-RFSG selects an internal synthesizer and the synthesizer signal is switched to both the RF In and RF Out mixers. This value is valid only on the PXIe-5830/5831/5832/5841 with PXIe-5655.
NIRFSG_VAL_LO_SOURCE_AUTOMATIC_SG_SA_SHARED_STR	NI-RFSG internally makes the configuration to share the LO between NI-RFSA and NI-RFSG. This value is valid only on the PXIe-5820/5830/5831/5832/5840/5841.
Default Value: NIRFSG_VAL_LO_SOURCE_ONBOARD_STR

Supported Devices: PXIe-5644/5645/5646, PXIe-5830/5831/5832/5840/5841

Related Topics

PXIe-5830 LO Sharing Using NI-RFSA and NI-RFSG

PXIe-5831/5832 LO Sharing Using NI-RFSA and NI-RFSG

Numeric Value	Data type	Access	Coercion	High Level Functions
1150144	ViInt32	R/W	None	None

Specifies the connector(s) to use to generate the signal. To set this attribute, the NI-RFSG device must be in the Configuration state.

You must write complex I and Q data for all options. The Q data has no effect if you set this attribute to I Only and set the NIRFSG_ATTR_IQ_OUT_PORT_CARRIER_FREQUENCY attribute to 0. If you set the NIRFSG_ATTR_IQ_OUT_PORT_CARRIER_FREQUENCY attribute to a value other than 0, the onboard signal processing (OSP) frequency shifts I and Q as a complex value and outputs the real portion of the result on the I connector(s) of the device.

If you set the NIRFSG_ATTR_OUTPUT_PORT attribute to NIRFSG_VAL_I_ONLY or NIRFSG_VAL_IQ_OUT, the NIRFSG_ATTR_IQ_OUT_PORT_TERMINAL_CONFIGURATION attribute applies.

Defined Values:

NIRFSG_VAL_RF_OUT	Enables the RF OUT port. This value is not valid for the PXIe-5820.
NIRFSG_VAL_IQ_OUT	Enables the I/Q OUT port. This value is valid on only the PXIe-5645 and PXIe-5820.
NIRFSG_VAL_CAL_OUT	Enables the CAL OUT port.
NIRFSG_VAL_I_ONLY	Enables the I connectors of the I/Q OUT port. This value is valid on only the PXIe-5645.
Default Value:

PXIe-5644/5645/5646, PXIe-5830/5831/5832/5840/5841: NIRFSG_VAL_RF_OUT

PXIe-5820: NIRFSG_VAL_IQ_OUT

Supported Devices: PXIe-5644/5645/5646, PXIe-5820/5830/5831/5832/5840/5841

Numeric Value	Data type	Access	Coercion	High Level Functions
1150220	ViReal64	R/W	None	None

Specifies the delay, in seconds, to apply to the I/Q waveform.

Relative delay allows for delaying the generated signal from one device relative to the generated signal of another device after those devices have been synchronized. You can achieve a negative relative delay by delaying both synchronized devices by the same value (1 μs) before generation begins and then changing the relative delay to a smaller amount than the initial value on only one of the devices.

	Note  To obtain a negative relative delay when synchronizing the PXIe-5840/5841 with a module that does not support this attribute, use the NITCLK_ATTR_SAMPLE_CLOCK_DELAY attribute.
To set this attribute, the NI-RFSG device must be in the Configuration or Generation state.

	Note  The resolution of this attribute is a function of the I/Q sample period at 15E(-6) of the sample period but not worse than one Sample Clock period.
Units: Seconds

Valid Values: 0 μs to 3.2 μs

Supported Devices: PXIe-5820/5830/5831/5832/5840/5841

Related Topics

NI-TClk Overview

Numeric Value	Data type	Access	Coercion	High Level Functions
1150162	ViString	R/W	None	None

Specifies the Marker Event at which RF blanking occurs. RF blanking quickly attenuates the RF OUT signal. Use Marker Events to toggle the state of RF blanking. The RF Output always starts in the unblanked state.

To set this attribute, the NI-RFSG device must be in the Configuration state.

You can specify Marker Events by using scripts to trigger blanking at a certain point in a waveform. For example, if you set this attribute to NIRFSG_VAL_MARKER0, and marker0 occurs on samples 1,000 and 2,000 of a script, then the RF Output will be blanked (attenuated) between samples 1,000 and 2,000.

	Note  The shortest supported blanking interval is eight microseconds.
PXIe-5645: This attribute is ignored if you are using the I/Q ports.

PXIe-5830/5831/5832: The only valid value for this attribute is "" (empty string).

PXIe-5840/5841: RF blanking does not occur for frequencies below 120 MHz.

Valid Values:

"" (empty string)	RF blanking is disabled.
NIRFSG_VAL_MARKER0	RF blanking is tied to marker0.
NIRFSG_VAL_MARKER1	RF blanking is tied to marker1.
NIRFSG_VAL_MARKER2	RF blanking is tied to marker2.
NIRFSG_VAL_MARKER3	RF blanking is tied to marker3.
Default Value: "" (empty string)

Supported Devices: PXIe-5644/5645/5646, PXIe-5830/5831/5832/5840/5841

Related Topics

Marker Events

Numeric Value	Data type	Access	Coercion	High Level Functions
1150241	ViString	R/W	None	None

Specifies the port to configure.

	Note  When using RF list mode, ports cannot be shared with NI-RFSA.
Valid Values:

PXIe-5644/5645/5646, PXIe-5820/5840/5841: "" (empty string)

PXIe-5830: if0, if1

PXIe-5831/5832: if0, if1, rf*<0-1>/port*, where 0-1 indicates one (0) or two (1) mmRH-5582 connections and x is the port number on the mmRH-5582 front panel.

Default Value:

PXIe-5644/5645/5646, PXIe-5820/5840/5841: "" (empty string)

PXIe-5830/5831/5832: if0

Supported Devices: PXIe-5820/5830/5831/5832/5840/5841

Related Topics

NIRFSG_ATTR_AVAILABLE_PORTS

Numeric Value	Data type	Access	Coercion	High Level Functions
1150249	ViString	RO	None	None

Returns a comma-separated list of the ports available for use based on your instrument configuration.

Supported Devices: PXIe-5644/5645/5646, PXIe-5820/5830/5831/5832/5840/5841

Data type	Access	Coercion	High Level Functions
ViString	R/W	None	None

Specifies which external trigger line distributes the Sample Clock sync signal. When synchronizing the Sample Clock between multiple devices, configure all devices to use the same Sample Clock sync distribution line.

To set this attribute, the NI-RFSG device must be in the Configuration state.

Valid Values: PXI_Trig0, PXI_Trig1, PXI_Trig2, PXI_Trig3, PXI_Trig4, PXI_Trig5, PXI_Trig6, PXI_Trig7, PFI0

Default Value: "" (empty string)

Supported Devices: PXIe-5646

Related Topics

Synchronization Using NI-RFSA and NI-RFSG—Refer to this topic for more information about PXIe-5646 device synchronization.

Data type	Access	Coercion	High Level Functions
ViBoolean	R/W	None	None

Specifies whether the device is the master device when synchronizing the Sample Clock between multiple devices. The master device distributes the Sample Clock sync signal to all devices in the system through the Sample Clock sync distribution line.

When synchronizing the Sample Clock, one device must always be designated as the master. The master device actively drives the Sample Clock sync distribution line.

To set this attribute, the NI-RFSG device must be in the Configuration state.

Defined Values:

VI_TRUE	The device is the master device for synchronizing the Sample Clock.
VI_FALSE	The device is not the master for synchronizing the Sample Clock.
Default Value: VI_FALSE

Supported Devices: PXIe-5646

Related Topics

Synchronization Using NI-RFSA and NI-RFSG—Refer to this topic for more information about PXIe-5646 device synchronization.

Numeric Value	Data type	Access	Coercion	High Level Functions
1150143	ViString	R/W	None	None

Specifies which external trigger line distributes the synchronized Script Trigger signal. When synchronizing the Script Trigger, configure all devices to use the same Script Trigger distribution line.

To set this attribute, the NI-RFSG device must be in the Configuration state.

Valid Values: PXI_Trig0, PXI_Trig1, PXI_Trig2, PXI_Trig3, PXI_Trig4, PXI_Trig5, PXI_Trig6, PXI_Trig7, PFI0

Default Value: "" (empty string)

Supported Devices: PXIe-5644/5645/5646

Related Topics

Script Trigger

Synchronizing Sample Clock and Sampled Reference Clock Signals

Refer to the Synchronization Using NI-RFSA and NI-RFSG topic appropriate to your device for more information about device synchronization for vector signal transceivers.

Numeric Value	Data type	Access	Coercion	High Level Functions
1150142	ViBoolean	R/W	None	None

Specifies whether the device is the master device when synchronizing the Script Trigger.

The master device distributes the synchronized Script Trigger to all devices in the system through the Script Trigger distribution line.

When synchronizing the Script trigger, one device must always be designated as the master. The master device actively drives the Script Trigger distribution line. For slave devices, set the NIRFSG_ATTR_SCRIPT_TRIGGER_TYPE attribute to NIRFSG_VAL_DIGITAL_EDGE, and set the NIRFSG_ATTR_DIGITAL_EDGE_SCRIPT_TRIGGER_SOURCE attribute to sync_script.

To set this attribute, the NI-RFSG device must be in the Configuration state.

Defined Values:

VI_TRUE	The device is the master device for synchronizing the Script Trigger.
VI_FALSE	The device is not the master for synchronizing the Script Trigger.
Default Value: VI_FALSE

Supported Devices: PXIe-5644/5645/5646

Related Topics

Script Trigger

Synchronizing Sample Clock and Sampled Reference Clock Signals

Refer to the Synchronization Using NI-RFSA and NI-RFSG topic appropriate to your device for more information about device synchronization for vector signal transceivers.

Numeric Value	Data type	Access	Coercion	High Level Functions
1150156	ViString	R/W	None	None

Specifies which external trigger line distributes the synchronized Start Trigger signal. When synchronizing the Start Trigger, configure all devices to use the same Start Trigger distribution line.

To set this attribute, the NI-RFSG device must be in the Configuration state.

Valid Values: PXI_Trig0, PXI_Trig1, PXI_Trig2, PXI_Trig3, PXI_Trig4, PXI_Trig5, PXI_Trig6, PXI_Trig7, PFI0

Default Value: "" (empty string)

Supported Devices: PXIe-5644/5645/5646

Related Topics

Start Trigger

Refer to the Synchronization Using NI-RFSA and NI-RFSG topic appropriate to your device for more information about device synchronization for vector signal transceivers.

Numeric Value	Data type	Access	Coercion	High Level Functions
1150155	ViBoolean	R/W	None	None

Specifies whether the device is the master device when synchronizing the Start Trigger. The master device distributes the synchronized Start Trigger to all devices in the system through the Start Trigger distribution line.

When synchronizing the Start Trigger, one device must always be designated as the master. The master device actively drives the Start Trigger distribution line. For slave devices, set the NIRFSG_ATTR_START_TRIGGER_TYPE attribute to NIRFSG_VAL_DIGITAL_EDGE, and set the NIRFSG_ATTR_DIGITAL_EDGE_START_TRIGGER_SOURCE attribute to sync_script.

To set this attribute, the NI-RFSG device must be in the Configuration state.

Defined Values:

VI_TRUE	The device is the master device for synchronizing the Start Trigger.
VI_FALSE	The device is not the master for synchronizing the Start Trigger.
Default Value: VI_FALSE

Supported Devices: PXIe-5644/5645/5646

Related Topics

Start Trigger

Refer to the Synchronization Using NI-RFSA and NI-RFSG topic appropriate to your device for more information about device synchronization for vector signal transceivers.

Numeric Value	Data type	Access	Coercion	High Level Functions
1150160	ViReal64	R/W	None	None

This attribute offsets the NIRFSG_ATTR_UPCONVERTER_CENTER_FREQUENCY from the RF frequency. Use this attribute to keep the local oscillator (LO) leakage at a determined offset from the RF signal.

	Note  You cannot set the NIRFSG_ATTR_UPCONVERTER_CENTER_FREQUENCY attribute or the NIRFSG_ATTR_ARB_CARRIER_FREQUENCY attribute at the same time as the NIRFSG_ATTR_UPCONVERTER_FREQUENCY_OFFSET attribute.

	Note  Resetting this attribute disables the upconverter frequency offset.
Valid Values:

PXIe-5644/5645: -42 MHz to 42 MHz

PXIe-5646: -100 MHz to 100 MHz

PXIe-5830/5831/5832/5840/5841: -625 MHz to 625 MHz

Supported Devices: PXIe-5644/5645/5646, PXIe-5830/5831/5832/5840/5841

Related Topics

PXIe-5830 Frequency and Bandwidth Selection

PXIe-5831/5832 Frequency and Bandwidth Selection

PXIe-5841 Frequency and Bandwidth Selection