• Vector Signal Transceiver
  • Signal Path
    • NIRFSA_ATTR_INPUT_PORT
    • NIRFSA_ATTR_LO_IN_POWER
    • NIRFSA_ATTR_LO_OUT_POWER
    • NIRFSA_ATTR_ABSOLUTE_DELAY
    • NIRFSA_ATTR_DECIMATION_DELAY
    • NIRFSA_ATTR_LO_FREQUENCY_STEP_SIZE
    • NIRFSA_ATTR_LO_VCO_FREQUENCY_STEP_SIZE
    • NIRFSA_ATTR_LO_PLL_FRACTIONAL_MODE_ENABLED
  • Acquisition
    • Advanced
      • NIRFSA_ATTR_DOWNCONVERTER_FREQUENCY_OFFSET
  • Triggers
    • Ref
      • IQ Analog Edge
        • NIRFSA_ATTR_IQ_ANALOG_EDGE_REF_TRIGGER_SOURCE
        • NIRFSA_ATTR_IQ_ANALOG_EDGE_REF_TRIGGER_HYSTERESIS
        • NIRFSA_ATTR_IQ_ANALOG_EDGE_REF_TRIGGER_SLOPE
        • NIRFSA_ATTR_IQ_ANALOG_EDGE_REF_TRIGGER_LEVEL
    • Synchronization
      • NIRFSA_ATTR_SYNC_START_TRIGGER_MASTER
      • NIRFSA_ATTR_SYNC_START_TRIGGER_DIST_LINE
      • NIRFSA_ATTR_SYNC_REF_TRIGGER_MASTER
      • NIRFSA_ATTR_SYNC_REF_TRIGGER_DIST_LINE
      • NIRFSA_ATTR_SYNC_ADVANCE_TRIGGER_MASTER
      • NIRFSA_ATTR_SYNC_ADVANCE_TRIGGER_DIST_LINE
      • NIRFSA_ATTR_SYNC_SAMPLE_CLOCK_MASTER
      • NIRFSA_ATTR_SYNC_SAMPLE_CLOCK_DIST_LINE
      • NIRFSA_ATTR_SYNC_REF_TRIGGER_DELAY_ENABLED
  • IQ In Port
    • NIRFSA_ATTR_IQ_IN_PORT_CARRIER_FREQUENCY
    • NIRFSA_ATTR_IQ_IN_PORT_VERTICAL_RANGE
    • NIRFSA_ATTR_IQ_IN_PORT_TERMINAL_CONFIGURATION
    • NIRFSA_ATTR_COMMON_MODE
    • NIRFSA_ATTR_IQ_IN_PORT_TEMPERATURE
  • Device Characteristics
    • NIRFSA_ATTR_FPGA_BITFILE_PATH
  • Noise Source Power Enabled
    • NIRFSA_ATTR_MAX_DEVICE_INSTANTANEOUS_BANDWIDTH
    • NIRFSA_ATTR_MAX_IQ_RATE
• NI 5606
  • NIRFSA_ATTR_NOISE_SOURCE_POWER_ENABLED

Data type	Access	High Level Functions
ViInt32	R/W	None

Specifies the connector(s) to use to acquire the signal. To set this attribute, the NI-RFSA device must be in the Configuration state.

Defined Values:

NIRFSA_VAL_RF_IN (2000)	Enables the RF IN port.
NIRFSA_VAL_IQ_IN (2001)	Enables the I/Q IN port.
NIRFSA_VAL_CAL_IN (2002)	Enables the CAL IN port.
NIRFSA_VAL_I_ONLY (2003)	Enables the I terminals of the I/Q IN port.
Default Values:

PXIe-5820: NIRFSA_VAL_IQ_IN

All other devices: NIRFSA_VAL_RF_IN

Supported Devices: PXIe-5644/5645/5646, PXIe-5820/5830/5831/5832/5840/5841

Data type	Access	High Level Functions
ViReal64	R/W	None

Returns the power level, in dBm, expected at the LO IN terminal when the NIRFSA_ATTR_LO_SOURCE attribute is set to NIRFSA_VAL_LO_IN_STR.

	Note  For the PXIe-5644/5645/5646, this attribute is always read-only.
Supported Devices: PXIe-5644/5645/5646, PXIe-5830/5831/5832/5840/5841

Data type	Access	High Level Functions
ViReal64	R/W	None

Specifies the power level, in dBm, of the signal at the LO OUT terminal when the NIRFSA_ATTR_EXPORT_ENABLED attribute is set to VI_TRUE.

To use this attribute for the PXIe-5830/5831/5832, you must use the channelName parameter of the niRFSA_SetAttributeViReal64 function to specify the name of the channel you are configuring. You can configure the LO1 and LO2 channels by using lo1 or lo2 as the channel string, or set the channel string to lo1,lo2 to configure both channels. For all other devices, the the only valid value for the channel string is "" (empty string).

Units: dBm

Supported Devices: PXIe-5830/5831/5832/5840/5841

Data type	Access	High Level Functions
ViReal64	R/W	None

Specifies the sub-sample clock delay, in seconds, to apply to the acquired signal. Use this attribute to reduce the trigger jitter when synchronizing multiple devices with NI-TClk. This attribute can also help maintain synchronization repeatability by writing the absolute delay value of a previous measurement to the current session.

To set this attribute, the NI-RFSA device must be in the Configuration state.

	Note  If this attribute is set, NI-TClk cannot do any sub-sample clock adjustment.
Units: Seconds

Valid Values: Plus or minus half of one sample clock period

Default Value: 0

Supported Devices: PXIe-5668, PXIe-5820/5830/5831/5832/5840/5841

Data type	Access	High Level Functions
ViReal64	R/W	None

Specifies the sub-sample delay, in seconds, to apply to the acquired signal. To set this attribute, the NI-RFSA device must be in the Configuration state.

Valid Values: -4.16 ns to +4.16 ns

Default Value: 0

Supported Devices: PXIe-5644/5645/5646

Data type	Access	High Level Functions
ViReal64	R/W	None

Specifies the step size for tuning the local oscillator (LO) phase-locked loop (PLL).

You can only tune the LO frequency by multiples of the NIRFSA_ATTR_LO_FREQUENCY_STEP_SIZE attribute. For the PXIe-5644/5645/5646 and PXIe-5840/5841, the LO frequency can therefore be offset from the requested center frequency by as much as half of the NIRFSA_ATTR_LO_FREQUENCY_STEP_SIZE attribute. This offset is corrected by digitally frequency shifting the NIRFSA_ATTR_LO_FREQUENCY attribute to the value requested in either the NIRFSA_ATTR_IQ_CARRIER_FREQUENCY attribute or the NIRFSA_ATTR_SPECTRUM_CENTER_FREQUENCY attribute.

	Note  For the PXIe-5831 with PXIe-5653 and PXIe-5832 with PXIe-5653, this attribute is ignored if the PXIe-5653 is used as the LO source.
The valid values for this attribute depend on the NIRFSA_ATTR_LO_PLL_FRACTIONAL_MODE_ENABLED attribute.

PXIe-5644/5645/5646—If the NIRFSA_ATTR_LO_PLL_FRACTIONAL_MODE_ENABLED attribute is set to NIRFSA_VAL_DISABLED, the specified value is coerced to the closest valid value.

PXIe-5840/5841—If the NIRFSA_ATTR_LO_PLL_FRACTIONAL_MODE_ENABLED attribute is set to NIRFSA_VAL_DISABLED, the specified value is coerced to the nearest valid value that is less than or equal to the desired step size.

NI_RFSA_ATTR_LO_PLL_FRACTIONAL_MODE_ENABLED Attribute Setting	LO Frequency Step Size Attribute Valid Values on PXIe-5644/5645	LO Frequency Step Size Attribute Valid Values on PXIe-5646	LO Frequency Step Size Attribute Valid Values on PXIe-5840/5841	LO Frequency Step Size Attribute Valid Values on PXIe-5830/5831/5832		LO Frequency Step Size Attribute Valid Values on PXIe-5841 with PXIe-5655*
				LO1	LO2
NIRFSA_VAL_ENABLED	50 kHz to 24 MHz	50 kHz to 25 MHz	50 kHz to 100 MHz	8 Hz to 400 MHz	4 Hz to 400 MHz	1 nHz to 50 MHz
NIRFSA_VAL_DISABLED	4 MHz, 5 MHz, 6 MHz, 12 MHz, 24 MHz	2 MHz, 5 MHz, 10 MHz, 25 MHz	1 MHz, 5 MHz, 10 MHz, 25 MHz, 50 MHz, 100 MHz	—	—
* Values up to 100 MHz are coerced to 50 MHz

|!Note) topic for more information about available ports for your hardware configuration. | | :- | :- | Default Values:

PXIe-5644/5645/5646: 200 kHz

PXIe-5830: 2 MHz

PXIe-5831/5832 (RF port): 8 MHz

PXIe-5831/5832 (IF port): 2 MHz, 4 MHz

PXIe-5840/5841:

• Fractional mode: 500 kHz
• Integer mode: 10 MHz for frequencies less than or equal to 4 GHz. 20 MHz for frequencies greater than 4 GHz.

PXIe-5841 with PXIe-5655: 500 kHz

Supported Devices: PXIe-5644/5645/5646, PXIe-5830/5831/5832/5840/5841

Data type	Access	High Level Functions
ViReal64	R/W	None

Specifies the step size for tuning the internal voltage-controlled oscillator (VCO) used to generate the LO signal.

	Note  Do not set this attribute with the NIRFSA_ATTR_LO_FREQUENCY_STEP_SIZE attribute.
Valid Values:

LO1: 1 Hz to 50 MHz

LO2: 1 Hz to 100 MHz

Default Values: 1 MHz

Supported Devices: PXIe-5830/5831/5832

Data type	Access	High Level Functions
ViInt32	R/W	None

Specifies whether to use fractional mode for the local oscillator (LO) phase-locked loop (PLL). Fractional mode gives a finer frequency step resolution, but it may result in non harmonic spurs. Refer to the device specifications for your device for more information about fractional mode and non harmonic spurs.

	Note  The NIRFSA_ATTR_LO_PLL_FRACTIONAL_MODE_ENABLED attribute is applicable only when using the internal LO.

Note  For the PXIe-5831 with PXIe-5653 and PXIe-5832 with PXIe-5653, this attribute is ignored if the PXIe-5653 is used as the LO source. For the PXIe-5841 with PXIe-5655, this attribute is ignored if the PXIe-5655 is used as the LO source.

To use this attribute for the PXIe-5830/5831/5832, you must use the channelName parameter of the niRFSA_SetAttributeViInt32 function to specify the name of the channel you are configuring. You can configure the LO1 and LO2 channels by using lo1 or lo2 as the channel string, or set the channel string to lo1,lo2 to configure both channels. For all other devices, the the only valid value for the channel string is "" (empty string).

Defined Values:

NIRFSA_VAL_DISABLED (1900)	The attribute is disabled.
NIRFSA_VAL_ENABLED (1901)	The attribute is enabled.
Default Value: NIRFSA_VAL_ENABLED

Supported Devices: PXIe-5644/5645/5646, PXIe-5830/5831/5832/5840/5841

Data type	Access	High Level Functions
ViReal64	R/W	None

Specifies an offset from the I/Q carrier frequency for the downconverter. If you set this attribute, any measurements outside the instantaneous bandwidth of the device are invalid. After you set this attribute, the RF downconverter is locked to that frequency offset until the value is changed or the attribute is reset.

Valid Values:

PXIe-5646: -100 MHz to +100 MHz

PXIe-5830/5831/5832/5840/5841: -625 MHz to +625 MHz

All other devices: -42 MHz to +42 MHz

Default Values: For spectrum acquisition types the driver automatically calculates the default to avoid residual LO power. For I/Q acquisition types the default is 0 Hz. If the center frequency is set to a non-multiple of the NIRFSA_ATTR_SIGNAL_PATH_LO_FREQUENCY_STEP_SIZE attribute, the NIRFSA_ATTR_DOWNCONVERTER_FREQUENCY_OFFSET attribute is set to compensate for the difference.

Supported Devices: PXIe-5644/5645/5646, PXIe-5830/5831/5832/5840/5841

Related Topics

PXIe-5830 Frequency and Bandwidth Selection

PXIe-5831/5832 Frequency and Bandwidth Selection

PXIe-5841 Frequency and Bandwidth Selection

Data type	Access	High Level Functions
ViString	R/W	None

Specifies the channel from which the device monitors the trigger. Use a value of "I" to monitor the I channel. Use a value of "Q" to monitor the Q channel. Use a value of "I,Q" to monitor both I and Q channels. This attribute affects the device operation only when the NIRFSA_ATTR_REF_TRIGGER_TYPE attribute is set to NIRFSA_VAL_IQ_ANALOG_EDGE.

Valid Values: "I", "Q", "I,Q", "Q,I"

Default Value: "I"

Supported Devices: PXIe-5644/5645

Data type	Access	High Level Functions
ViReal64	R/W	None

Specifies the size of the hysteresis window on either side of the trigger level. The device triggers when the signal passes through the threshold you specify with the NIRFSA_ATTR_IQ_ANALOG_EDGE_REF_TRIGGER_LEVEL attribute, has the slope you specify with the NIRFSA_ATTR_IQ_ANALOG_EDGE_REF_TRIGGER_SLOPE attribute, and passes through the hysteresis window that you specify with this attribute. This attribute affects the device operation only when the NIRFSA_ATTR_REF_TRIGGER_TYPE attribute is set to NIRFSA_VAL_IQ_ANALOG_EDGE.

Valid Values: 0 to (Voltage Range/2 + Trigger Level) for Rising Slope. 0 to (Voltage Range/2 – Trigger Level) for Falling Slope. These values limit the hysteresis to the entire voltage range that is below the trigger level for Rising Slope or that is above the trigger level for Falling Slope.

Default Value: The default is calculated by the driver as (Range x 0.025).

Supported Devices: PXIe-5644/5645R

Data type	Access	High Level Functions
ViInt32	R/W	None

Specifies whether the device asserts the trigger when the voltage level is rising or falling. When you set the NIRFSA_ATTR_REF_TRIGGER_TYPE attribute to NIRFSA_VAL_IQ_ANALOG_EDGE, the device asserts the trigger when the signal level exceeds the specified level with the slope you specify. This attribute affects the device operation only when the NIRFSA_ATTR_REF_TRIGGER_TYPE attribute is set to NIRFSA_VAL_IQ_ANALOG_EDGE.

Defined Values:

NIRFSA_VAL_RISING_SLOPE (1000)	The trigger asserts when the signal power is rising.
NIRFSA_VAL_FALLING_SLOPE (1001)	The trigger asserts when the signal power is falling.
Default Value: NIRFSA_VAL_RISING_SLOPE

Supported Devices: PXIe-5644/5645

Data type	Access	High Level Functions
ViReal64	R/W	None

Specifies the analog level, in volts, at which the device triggers. The device asserts the trigger when the signal exceeds the level specified by the value of this attribute, taking into consideration the specified slope. This attribute affects the device operation only when the NIRFSA_ATTR_REF_TRIGGER_TYPE attribute is set to NIRFSA_VAL_IQ_ANALOG_EDGE.

Default Value: 0 V

Supported Devices: PXIe-5644/5645

Data type	Access	High Level Functions
ViBoolean	R/W	None

Specifies whether the device is the master for synchronizing the shared Start Trigger between multiple devices. The master device distributes the synchronized Start Trigger to all devices in the system through the Start Trigger distribution line.

When synchronizing the Start Trigger, one device must always be designated as the master. When the device is configured as a master, it actively drives the Start Trigger distribution line. When the device is configured as a slave, set the NIRFSA_ATTR_START_TRIGGER_TYPE attribute to NIRFSA_VAL_DIGITAL_EDGE, and the NIRFSA_ATTR_DIGITAL_EDGE_START_TRIGGER_SOURCE attribute to NIRFSA_VAL_SYNC_START_TRIGGER_STR.

Refer to the Synchronization Using NI-RFSA and NI-RFSG topic appropriate to your device in the NI RF Vector Signal Analyzers Help for more information about device synchronization for vector signal transceivers.

Defined Values:

VI_TRUE	The device is the master device for synchronizing the Start Trigger.
VI_FALSE	The device is not the master device for synchronizing the Start Trigger.
Default Value: VI_FALSE

Supported Devices: PXIe-5644/5645/5646

Data type	Access	High Level Functions
ViString	R/W	None

Specifies which external trigger line distributes the synchronized Start Trigger signal. When synchronizing the Start Trigger, configure all devices to use the same Start Trigger distribution line.

Refer to the Synchronization Using NI-RFSA and NI-RFSG topic appropriate to your device in the NI RF Vector Signal Analyzers Help for more information about device synchronization for vector signal transceivers.

Valid Values: PXI_Trig0, PXI_Trig1, PXI_Trig2, PXI_Trig3, PXI_Trig4, PXI_Trig5, PXI_Trig6, PXI_Trig7, PFI0

Default Value: "" (empty string)

Supported Devices: PXIe-5644/5645/5646

Data type	Access	High Level Functions
ViBoolen	R/W	None

Specifies whether the device is the master for synchronizing the shared Reference Trigger between multiple devices. The master device distributes the synchronized Reference Trigger to all devices in the system through the Reference Trigger distribution line.

When synchronizing the Reference Trigger, one device must always be designated as the master. When the device is configured as a master, it actively drives the Reference Trigger distribution line. When the device is configured as a slave, set the NIRFSA_ATTR_REF_TRIGGER_TYPE attribute to NIRFSA_VAL_DIGITAL_EDGE, and the NIRFSA_ATTR_DIGITAL_EDGE_REF_TRIGGER_SOURCE attribute to NIRFSA_VAL_SYNC_REF_TRIGGER_STR.

Refer to the Synchronization Using NI-RFSA and NI-RFSG topic appropriate to your device in the NI RF Vector Signal Analyzers Help for more information about device synchronization for vector signal transceivers.

Defined Values:

VI_TRUE	The device is the master device for synchronizing the Ref Trigger.
VI_FALSE	The device is not the master device for synchronizing the Ref Trigger.
Default Value: VI_FALSE

Supported Devices: PXIe-5644/5645/5646

Data type	Access	High Level Functions
ViString	R/W	None

Specifies which external trigger line distributes the synchronized Reference Trigger signal. When synchronizing the Reference Trigger, configure all devices to use the same Reference Trigger distribution line.

Refer to the Synchronization Using NI-RFSA and NI-RFSG topic appropriate to your device in the NI RF Vector Signal Analyzers Help for more information about device synchronization for vector signal transceivers.

Valid Values: PXI_Trig0, PXI_Trig1, PXI_Trig2, PXI_Trig3, PXI_Trig4, PXI_Trig5, PXI_Trig6, PXI_Trig7, PFI0

Default Value: "" (empty string)

Supported Devices: PXIe-5644/5645/5646

Data type	Access	High Level Functions
ViBoolean	R/W	None

Specifies whether the device is the master for synchronizing the shared Advance Trigger between multiple devices. The master device distributes the synchronized Advance Trigger to all devices in the system through the Advance Trigger distribution line.

When synchronizing the Advance Trigger, one device must always be designated as the master. When the device is configured as a master, it actively drives the Advance Trigger distribution line. When the device is configured as a slave, set the NIRFSA_ATTR_ADVANCE_TRIGGER_TYPE attribute to NIRFSA_VAL_DIGITAL_EDGE, and the NIRFSA_ATTR_DIGITAL_EDGE_ADVANCE_TRIGGER_SOURCE attribute to NIRFSA_VAL_SYNC_ADVANCE_TRIGGER_STR.

Refer to the Synchronization Using NI-RFSA and NI-RFSG topic appropriate to your device in the NI RF Vector Signal Analyzers Help for more information about device synchronization for vector signal transceivers.

Defined Values:

VI_TRUE	The device is the master device for synchronizing the Advance Trigger.
VI_FALSE	The device is not the master device for synchronizing the Advance Trigger.
Default Value: VI_FALSE

Supported Devices: PXIe-5644/5645/5646

Data type	Access	High Level Functions
ViString	R/W	None

Specifies which external trigger line distributes the synchronized Advance Trigger signal. When synchronizing the Advance Trigger, configure all devices to use the same Advance Trigger distribution line.

Refer to the Synchronization Using NI-RFSA and NI-RFSG topic appropriate to your device in the NI RF Vector Signal Analyzers Help for more information about device synchronization for vector signal transceivers.

Valid Values: PXI_Trig0, PXI_Trig1, PXI_Trig2, PXI_Trig3, PXI_Trig4, PXI_Trig5, PXI_Trig6, PXI_Trig7, PFI0

Default Value: "" (empty string)

Supported Devices: PXIe-5644/5645/5646

Data type	Access	Coercion	High Level Functions
ViBoolean	R/W	None	None

Specifies whether the device is the master device for synchronizing the Sample Clock between multiple devices. The master device distributes the Sample Clock sync signal to all devices in the system through the Sample Clock sync distribution line.

When synchronizing the Sample Clock, one device must always be designated as the master. The master device actively drives the Sample Clock sync distribution line.

Refer to Synchronization Using NI-RFSA and NI-RFSG for more information about PXIe-5646 device synchronization.

Defined Values:

VI_TRUE	The device is the master device for synchronizing the Sample Clock.
VI_FALSE	The device is not the master for synchronizing the Sample Clock.
Default Value: VI_FALSE

Supported Devices: PXIe-5646

Data type	Access	Coercion	High Level Functions
ViString	R/W	None	None

Specifies which external trigger line distributes the Sample Clock sync signal. When synchronizing the Sample Clock, configure all devices to use the same Sample Clock distribution line.

Refer to Synchronization Using NI-RFSA and NI-RFSG for more information about PXIe-5646 device synchronization.

Valid Values: PXI_Trig0, PXI_Trig1, PXI_Trig2, PXI_Trig3, PXI_Trig4, PXI_Trig5, PXI_Trig6, PXI_Trig7, PFI0

Default Value: "" (empty string)

Supported Devices: PXIe-5646

Data type	Access	High Level Functions
ViInt32	R/W	None

Specifies whether the Reference Trigger is delayed with the data. Set this attribute to NIRFSA_VAL_DISABLED when the NIRFSA_ATTR_REF_TRIGGER_TYPE attribute is set to NIRFSA_VAL_IQ_POWER_EDGE or NIRFSA_VAL_IQ_ANALOG_EDGE.

Refer to the Synchronization Using NI-RFSA and NI-RFSG topic appropriate to your device in the NI RF Vector Signal Analyzers Help for more information about device synchronization for vector signal transceivers.

Defined Values:

NIRFSA_VAL_DISABLED (1900)	The attribute is disabled.
NIRFSA_VAL_ENABLED (1901)	The attribute is enabled.
Default Value: NIRFSA_VAL_DISABLED

Supported Devices: PXIe-5644/5645/5646

Data type	Access	High Level Functions
ViReal64	R/W	None

Configures the frequency of the signal. The onboard signal processing (OSP) frequency shifts the signal at this frequency to baseband prior to acquiring it.

	Note  For the PXIe-5645, this attribute is ignored if you are using the RF ports.
Valid Values:

PXIe-5645: -60 MHz to +60 MHz

PXIe-5820: -500 MHz to +500 MHz

Default Value: 0

Supported Devices: PXIe-5645, PXIe-5820

Data type	Access	High Level Functions
ViReal64	R/W	None

Specifies the voltage range for the I/Q terminals.

To use this attribute, you must use the channelName parameter of the niRFSA_SetAttributeViReal64 function to specify the name of the channel you are configuring. For the PXIe-5645, you can configure the I and Q channels by using I or Q as the channel string, or set the channel string to "" (empty string) to configure both channels. For the PXIe-5820, the only valid value for the channel string is "" (empty string).

The voltage range in differential terminal configuration is configurable from 2 Vpk-pk to 0.032 Vpk-pk in 1 dB steps. In single-ended terminal configuration, valid ranges are half those for differential. Values are always coerced up to the next valid range.

	Note  For the PXIe-5645, this attribute is ignored if you are using the RF ports.
Valid Values:

PXIe-5645: 0 Vpk-pk to 2 Vpk-pk for differential terminal configuration, 0 Vpk-pk to 1 Vpk-pk for single-ended terminal configuration.

PXIe-5820: 0 Vpk-pk to 4 Vpk-pk for differential terminal configuration.

Default Value: 2 Vpk-pk

Supported Devices: PXIe-5645, PXIe-5820

Data type	Access	High Level Functions
ViInt32	R/W	None

Configures the terminal configuration of the I/Q port.

To use this attribute, you must use the channelName parameter of the niRFSA_SetAttributeViInt32 function to specify the name of the channel you are configuring. For the PXIe-5645, you can configure the I and Q channels by using I or Q as the channel string, or set the channel string to "" (empty string) to configure both channels. For the PXIe-5820, the only valid value for the channel string is "" (empty string).

	Note  For the PXIe-5645, this attribute is ignored if you are using the RF ports.
PXIe-5820—The only valid value for this attribute is NIRFSA_VAL_DIFFERENTIAL.

Defined Values:

NIRFSA_VAL_DIFFERENTIAL (2100)	Sets the terminal configuration to differential.
NIRFSA_VAL_SINGLE_ENDED (2101)	Sets the terminal configuration to single-ended.
Default Value: NIRFSA_VAL_DIFFERENTIAL

Supported Devices: PXIe-5645, PXIe-5820

Data type	Access	High Level Functions
ViReal64	R/W	None

Specifies the common-mode level presented at each differential input terminal. Common-mode level shifts both positive and negative terminals in the same direction. This must match the common-mode level of the device under test (DUT).

Units: volts

Default Value: 0 V

Supported Devices: PXIe-5820

Data type	Access	High Level Functions
ViReal64	RO	None

Returns the temperature of the I/Q IN circuitry on the device.

Units: degrees C

Supported Devices: PXIe-5645, PXIe-5820

Data type	Access	Coercion	High Level Functions
ViString	RO	None	None

Returns a string containing the path to the location of the current NI-RFSA instrument driver FPGA extensions bitfile, a .lvbitx file, that is programmed on the device. You can specify the bitfile location using the Driver Setup string in the optionString parameter of the niRFSA_InitWithOptions function.

NI-RFSA instrument driver FPGA extensions enable you to use pre-compiled FPGA bitfiles to customize the behavior of the device FPGA while maintaining the functionality of the NI-RFSA instrument driver.

Refer to NI-RFSA Instrument Driver FPGA Extensions for more information about using NI-RFSA instrument driver FPGA extensions for NI devices.

Supported Devices: PXIe-5644/5645/5646, PXIe-5668, PXIe-5820/5830/5831/5832/5840/5841

Data type	Access	High Level Functions
ViReal64	R	N/A

Returns the maximum instantaneous bandwidth of the device.

Default Value: N/A

Supported Devices: PXI-5600, PXIe-5601/5603/5605/5606 (external digitizer mode), PXIe-5644/5645/5646, PXI-5661, PXIe-5663/5663E/5665/5667/5668, PXIe-5693/5694, PXIe-5820/5830/5831/5832/5840/5841

Data type	Access	High Level Functions
ViReal64	R	N/A

Returns the maximum I/Q rate.

Default Value: N/A

Supported Devices: PXIe-5644/5645/5646, PXI-5661, PXIe-5663/5663E/5665/5667/5668, PXIe-5820/5830/5831/5832/5840/5841

Data type	Access	High Level Functions
ViReal64	R/W	None

Enables the 28 V DC source on the device front panel.

PXIe-5668 with PXIe-5698—When this attribute is set to NIRFSA_VAL_ENABLED, the PXIe-5698 noise source is used instead of the PXIe-5668 noise source.

Units: dB

Default Value: NIRFSA_VAL_DISABLED

Supported Devices: PXIe-5606, PXIe-5668, PXIe-5698