Adding Baseband Modem to Digital Workspace - neu-ucb-tvip/barduino-vlsi GitHub Wiki

Here are the steps to adding the baseband modem to the digital workspace.

1. Copy generators/baseband and generators/dma into your repo

2. Add WithBasebandModemPunchthrough class to IObinders.scala

import baseband.{CanHavePeripheryBasebandModem, BasebandModemAnalogIO, BasebandModemIntraIO, BasebandModemParams}
class WithBasebandModemPunchthrough(params: BasebandModemParams = BasebandModemParams()) extends OverrideIOBinder({
  (system: CanHavePeripheryBasebandModem) => {
    val chiptop_clock_port = IO(Input(Clock())).suggestName("bm_clock_in")

    val clockPort = if (system.analog_bm_clock_pin != null) {
      system.analog_bm_clock_pin := chiptop_clock_port
      Seq(ClockPort(() => chiptop_clock_port, freqMHz = 32.0))
    } else {
      chiptop_clock_port := false.B.asClock
      Nil
    }

    val (bmPorts, cells) = system.bm_ios.map { a =>
      val io = IO(new BasebandModemIntraIO(params)).suggestName("bm_block")

      // Tie off the IO *in ChipTop*, so elaboration passes
      io.lo_div8_clock := false.B
      io.data.rx.i.data := 0.U
      io.data.rx.q.data := 0.U
      io.data.rx.i.valid := false.B
      io.data.rx.q.valid := false.B
      io.tuning.trim.g1 := 0.U


      a.intra.lo_div8_clock := io.lo_div8_clock
      a.intra.data.rx.i.data := io.data.rx.i.data
      a.intra.data.rx.q.data := io.data.rx.q.data
      a.intra.data.rx.i.valid := io.data.rx.i.valid
      a.intra.data.rx.q.valid := io.data.rx.q.valid
      a.intra.data.tx <> io.data.tx
      a.intra.data.tuning <> io.data.tuning
      a.intra.tuning.trim.g1 := io.tuning.trim.g1

      (Seq(BasebandModemAnalogPort(() => io)), Nil) // no bump cells
    }.getOrElse((Nil, Nil))

    (bmPorts ++ clockPort, cells)
  }
})

3. Add WithBasebandModemTiedOff to HarnessBinders.scala

import baseband.{CanHavePeripheryBasebandModem, BasebandModemAnalogIO}

class WithBasebandModemTiedOff extends HarnessBinder({
  // (system: CanHavePeripheryBasebandModem, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
    case (th: HasHarnessInstantiators, port: BasebandModemAnalogPort, chipId: Int) => {

    val lo_div8ClockFreqMHz: Double = 600.0
    val lo_div8ClkBundle = th.harnessClockInstantiator.requestClockMHz("lo_div8ClkBundle", lo_div8ClockFreqMHz)

    port.io.lo_div8_clock := lo_div8ClkBundle.asBool

    port.io.data.rx.i.data := 0.U
    port.io.data.rx.q.data := 0.U
    port.io.data.rx.i.valid := 0.U
    port.io.data.rx.q.valid := 0.U
    port.io.tuning.trim.g1 := 0.U

  }
})

4. Add BasebandModemAnalogPort to Ports.scala

import baseband.{BasebandModemAnalogIO, BasebandModemIntraIO, BasebandModemParams}
case class BasebandModemAnalogPort  (val getIO: () => BasebandModemIntraIO)
    extends Port[BasebandModemIntraIO]

5. Add these lines to your Config

new baseband.WithBasebandModem() ++
  new chipyard.iobinders.WithBasebandModemPunchthrough() ++
  new chipyard.harness.WithBasebandModemTiedOff ++

6. Add these lines to your ChipTop

// Tie off inside module body 
  InModuleBody {
    system.bm_ios.foreach { io =>
      val a = io.getWrappedValue
      a.intra.lo_div8_clock := false.B
      a.intra.data.rx.i.data := 0.U
      a.intra.data.rx.q.data := 0.U
      a.intra.data.rx.i.valid := false.B
      a.intra.data.rx.q.valid := false.B
      a.intra.tuning.trim.g1 := 0.U
    }

    if (system.analog_bm_clock_pin != null) {
      system.analog_bm_clock_pin := false.B.asClock
    }
  }

7. Add this line to your DigitalTop

  with baseband.CanHavePeripheryBasebandModem // Enables optionally adding the BasebandModem periphery

8. Make sure you have this in your build.sbt file

lazy val chipyard = (project in file("generators/chipyard"))
  .dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
    dsptools, rocket_dsp_utils,
    gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
    constellation, mempress, barf, shuttle, caliptra_aes, rerocc,
    compressacc, saturn, dma, baseband, ara, firrtl2_bridge, vexiiriscv)
  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(
    libraryDependencies ++= Seq(
      "org.reflections" % "reflections" % "0.10.2"
    )
  )


lazy val dma = (project in file("generators/dma"))
  .dependsOn(rocketchip)
  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)


lazy val baseband = (project in file("generators/baseband"))
  .dependsOn(dma, fixedpoint)
  .settings(chiselSettings)
  .settings(commonSettings)