Multicomp compilation log - nealcrook/multicomp6809 GitHub Wiki

# ERROR: No extended dataflow license exists
# do MicrocomputerPCB_run_msim_rtl_vhdl.do
# if {[file exists rtl_work]} {
#     vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying /home/me/altera/13.0sp1/modelsim_ase/linuxaloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied /home/me/altera/13.0sp1/modelsim_ase/linuxaloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
#
# vcom -93 -work work {/home/me/altera/multicomp/Components/MMAPPER2/mem_mapper2.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity mem_mapper2
# -- Compiling architecture rtl of mem_mapper2
# vcom -93 -work work {/home/me/altera/multicomp/Components/GPIO/gpio.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity gpio
# -- Compiling architecture rtl of gpio
# vcom -93 -work work {/home/me/altera/multicomp/Components/TERMINAL/DisplayRam1K.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity DisplayRam1K
# -- Compiling architecture SYN of displayram1k
# vcom -93 -work work {/home/me/altera/multicomp/Components/TERMINAL/DisplayRam2K.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity DisplayRam2K
# -- Compiling architecture SYN of displayram2k
# vcom -93 -work work {/home/me/altera/multicomp/Components/TERMINAL/CGABoldRomReduced.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity CGABoldRomReduced
# -- Compiling architecture SYN of cgaboldromreduced
# vcom -93 -work work {/home/me/altera/multicomp/Components/TERMINAL/CGABoldRom.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity CGABoldRom
# -- Compiling architecture SYN of cgaboldrom
# vcom -93 -work work {/home/me/altera/multicomp/Components/M6809p/cpu09p.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity cpu09p
# -- Compiling architecture rtl of cpu09p
# vcom -93 -work work {/home/me/altera/multicomp/Components/SDCARD/sd_controller.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity sd_controller
# -- Compiling architecture rtl of sd_controller
# vcom -93 -work work {/home/me/altera/multicomp/Components/UART/bufferedUART.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity bufferedUART
# -- Compiling architecture rtl of bufferedUART
# vcom -93 -work work {/home/me/altera/multicomp/MicrocomputerPCB/InternalRam2K.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity InternalRam2K
# -- Compiling architecture SYN of internalram2k
# vcom -93 -work work {/home/me/altera/multicomp/ROMS/6809/M6809_CAMELFORTH_ROM.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity M6809_CAMELFORTH_ROM
# -- Compiling architecture SYN of m6809_camelforth_rom
# vcom -93 -work work {/home/me/altera/multicomp/Components/TERMINAL/SBCTextDisplayRGB.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity SBCTextDisplayRGB
# -- Compiling architecture rtl of SBCTextDisplayRGB
# -- Loading entity CGABoldRom
# -- Loading entity CGABoldRomReduced
# -- Loading entity DisplayRam2K
# -- Loading entity DisplayRam1K
# vcom -93 -work work {/home/me/altera/multicomp/MicrocomputerPCB/Microcomputer.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity Microcomputer
# -- Compiling architecture struct of Microcomputer
# -- Loading entity cpu09p
# -- Loading entity M6809_CAMELFORTH_ROM
# -- Loading entity InternalRam2K
# -- Loading package NUMERIC_STD
# -- Loading entity SBCTextDisplayRGB
# ** Warning: /home/me/altera/multicomp/MicrocomputerPCB/Microcomputer.vhd(331): Cannot associate port "hSync" of mode BUFFER with port "hSync" of mode OUT.
# ** Warning: /home/me/altera/multicomp/MicrocomputerPCB/Microcomputer.vhd(331): Cannot associate port "vSync" of mode BUFFER with port "vSync" of mode OUT.
# ** Warning: /home/me/altera/multicomp/MicrocomputerPCB/Microcomputer.vhd(331): Cannot associate port "video" of mode BUFFER with port "video" of mode OUT.
# -- Loading entity bufferedUART
# -- Loading entity sd_controller
# -- Loading entity mem_mapper2
# -- Loading entity gpio
#

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