Topic MiniPCIe - myazzurro/msr-wiki GitHub Wiki

###Intro

###LogiCORE IP AXI Bridge for PCI Express
This core provides an interface between an AXI4 customer user interface and PCI Express using the Xilinx Integrated Block for PCI Express. The AXI Bridge for PCI Express core provides the translation level between the AXI4 embedded system to the PCI Express system. The AXI Bridge for PCI Express core translates the AXI4 memory read or writes to PCIe Transaction Layer Packets (TLP) packets and translates PCIe memory read and write request TLP packets to AXI4 interface commands.

#####Typical Configuration
v2.3 Vivado2013.4

• PCIE: Basics
  • Select Root Port of PCI Express Root Complex for Device/Port Type
  • Select 100MHz for Reference Clock Freqency
  • Check Enable Slot Clock Configuration for Link Status Register

• PCIE: Link Config
  • Select X0Y0 for PCIe Block Location
  • Select X1 for Number of Lanes
  • Select 5.0 GT/s for Link Speed

• PCIE: ID
  • Vendor ID is 0x10EE
  • Device ID is 0x7012
  • Class Code is 0x060400

• PCIE: BARS
  • Enable ONLY the BAR0 with the size 16 Kilobytes

• PCIE: Misc
  • Select 50ms for Completion Timeout Configuration

• AXI:BARS

• AXI:System

• Shared Logic

• Address Base and Range