Topic Ethernet 10G - myazzurro/msr-wiki GitHub Wiki

###LogiCORE IP AXI 10-Gigabit Ethernet
This core integrates two cores (Xilinx LogiCORE IP 10-Gigabit Ethernet MAC and Xilinx LogiCORE IP 10-Gigabit Ethernet PCS/PMA)and adds a high accuracy timestamping capability compatible with IEEE1588-2008 (also known as IEEE1588v2).

#####LogiCORE IP 10-Gigabit Ethernet PCS/PMA
10GBASE-R/KR is a 10 Gb/s serial interface. It is intended to provide the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) functionality between the 10-Gigabit Media Independent Interface (XGMII) interface on a Ten Gigabit Ethernet Media Access Controller (MAC) and a Ten Gigabit Ethernet network physical-side interface (PHY).

#####LogiCORE IP 10-Gigabit Ethernet MAC
A fully verified solution for the 10-Gigabit per second (Gb/s) Ethernet Media Access Controller function that interfaces to physical layer devices in a 10 Gb/s Ethernet system. The core is designed to the IEEE Standard 802.3-2008 specification and supports the high-bandwidth demands of network Internet Protocol (IP) traffic on LAN, MAN, and WAN networks.

#####Typical Configuration
v3.0 Vivado2015.1

• Ethernet Standard
  • Select BASE-R for PCS/PMA Standard
  • Select 62bit * 156.25MHz solution for AXI4-Stream datapath width

• MAC Options
  • Check AXI4-Lite for Configuration and Status running at 75MHz
  • Check Statistics Gathering
  • Uncheck IEEE802.Qbb Priority-based Flow Control

• PCS/PMA Options
  • Choose 125.00MHz for DRP Clocking
  • Uncheck Additional transceiver DRP ports
  • Uncheck Additional transceiver control and status ports

• IEEE1588 Options

• Shared Logic
  • Select Include Shared Logic in Core for the 1st 10G port.
  • Select No Shared Logic in Core for the remaining 3 10G ports.