GSG DDR3MemTest - myazzurro/msr-wiki GitHub Wiki

###Intro
This project set is for ONetSwitch30 DDR3 on Zynq PL side only, implementing an example design to show the write/read process.

Demo runs at u-boot level.

###Project List

Board	Project
ONetSwitch20	`N/A`
ONetSwitch30	ons30-gsg-5-mddr_test
ONetSwitch45	`N/A`

###Pre-Built Images

For quick start demo.

File	ONetSwitch20	ONetSwitch30	ONetSwitch45
boot.bin	`N/A`	`Download`	`N/A`
devicetree	`N/A`	`N/A`	`N/A`
kernel	`N/A`	`N/A`	`N/A`
rootfs (FAT)	`N/A`	`N/A`	`N/A`
sw-lib	`N/A`	`N/A`	`N/A`
sw-app	`N/A`	`N/A`	`N/A`

For image assembling.

File	ONetSwitch20	ONetSwitch30	ONetSwitch45
system.bit	`N/A`	`Download`	`N/A`
fsbl	`N/A`	`Download`	`N/A`
u-boot (FAT)	`N/A`	`Download`	`N/A`
u-boot (EXT)	`N/A`	`Download`	`N/A`
rootfs (EXT)	`N/A`	`N/A`	`N/A`

###Target

Check the calibration-done signal for PL DDR3.
Read/Write the DDR3 using u-boot commands.

###Design Outline

VVD Create a simple ZYNQ7 system with Processing System 7 and Processor System Reset Module.
VVD Add a Memory Interface Generator with the DDR pin assignment specified in the hardware spec.
VVD Manage the generated DDR3 controller with an AXI GP interface, using AXI Interconnect.
VVD Button and LED indicators

SW5: Manual reset.
DS8: 125MHz clock from the Processing System.
DS9: MMCM lock, active high.
DS10: calibration-done, active high.
DS11: system reset, active low.

###Demo

Prepare the images in SD/TF card, or download the pre-built ones.
Check the LEDs, especially DS9 MMCM lock then DS10 the calibration should be done.
Reset it with button SW5 and then release the reset, the calibration-done would recover.
Read/Write the DDR3 by typing the md/mw command in the u-boot.