System Verilog Examples - muneeb-mbytes/verilator GitHub Wiki

In this page you can find some simple examples to understand VERILATOR tool

Step 1: Open Verilator tool

Step 2: Open the terminal

Step 3: Write a design file

module dff(clk,reset,d,out);
input wire clk,reset,d;
output reg out;

always@(posedge clk)
begin
    if(!reset)
        out<=0;
    else
        out<=d;
end
endmodule

Step 4: Write a testbench to test your design

`timescale 1ns/1ns
`include "dff.sv"
module dff_tb;
reg clk,reset,d;
wire out;

dff d1(.clk(clk),.reset(reset),.d(d),.out(out));

initial begin
clk=1'b0;
forever #5 clk=~clk;
end

initial begin
$dumpfile("dump.vcd");
$dumpvars();

reset=1'b0;
#5 reset=1'b0;
#5 reset=1'b1;
#10 d=1;
#10 d=0;
#5 d=1;
#15 d=1;

$display("This is D Flip flop code");

#500 $finish;
end
endmodule

Step 5: To run, Follow this below two commands

Command 1: verilator --binary --trace [testbench_file_name]

verilator --binary --trace dff_tb.sv

• It creates a new directory called obj_dir which contains executable file.

--binary: telling Verilator to do everything needed to create a simulation executable

--trace : To get the waveform

Command 2: ./obj_dir/V[testbench_file_name]

./obj_dir/Vdff_tb

Upon running the executable file using the above command we get the display statement containing message “This is D Flip flop code”.

For the above code you will see this output:

Step 6: Now to see the waveform, Follow the below command

gtkwave [waveform_filename]

gtkwave dump.vcd