Welcome to the RISC-V_Processor wiki!

Design of a RISC V based processor to implement the below operations :

1. Addition
2. Subtraction
3. Logical operations (OR, AND, XOR etc)
4. Comparision

RISC V PROCESSOR

PROCESSOR.v

It is the top module of RISC 5 processor Here Instantiating the CONTROL ,DATAPATH, IFU module is done

IFU.v:(Instruction fetch unit)

• The instruction fetch unit has clock and reset pins as input and 32-bit instruction code as output.
• Internally the block has Instruction Memory, Program Counter(P.C) and an adder to increment counter by 4, on every positive clock edge.

Instruction Memory:

It has 2 inputs

• 32-bit Program Counter (PC)

• Reset

Output

• 32-bit instruction code

It also has a Byte addressable memory with 32 locations used to assign to the instruction code

If reset = 1 => memory is initialized to a 32-bit value

For each of the operation (like add, sub etc.) we have to set the opcode and function bits

Setting 32-bit instruction: add t1, s0,s1 => 0x00940333

        Memory [3] = 8'h00;
        Memory [2] = 8'h94;
        Memory [1] = 8'h03;
        Memory [0] = 8'h33;   

This Memory will hold the 32-bit instruction values of all the operation. If we decode the above initialization which is in hexadecimal format to binary we will get the corresponding field values

        Memory [3] = 8'h00    = 8'b0000_0000
        Memory [2] = 8'h94    = 8'b1001_0100
        Memory [1] = 8'h03    = 8'b0000_0011
        Memory [0] = 8'h33    = 8'b0011_0011

R-format:

If reset = 0 => based on PC value, 32-bit instruction code is output

Register File:

It can read 2 registers and write to one register This register file has total 32 registers each of 32-bit size 5-bits are used to specify the register numbers that needs to be read or written

Inputs:

• 5-bit read reg1

• 5-bit read reg2

• 5-bit write reg

• 32-bit write data

• 1 bit regwite

• 1-bit clock

• 1-bit reset

Output:

• 32-bit read data1

• 32-bit read data2

In addition, it has 32 memory location each of 32-bit wide

Register Read:

• Register file always outputs the contents of the register corresponding to read register numbers specified.

• Reading a register is not dependent on any other signals.

Register Write:

• Register writes are controlled by a control signal RegWrite.

• Additionally, the register file has a clock signal.

• The write should happen if RegWrite signal is made 1 and if there is positive edge of clock.

• When reset is triggered reg memory is initialized with some value.

ALU.v

• ALU module takes two operands of size 32-bits each and a 4-bit ALU_control as input.

• Operation is performed on the basis of ALU_control value.

    000 Add(A+B)
  
    001 Subtract (A-B)
  
    010 Bitwise-AND
  
    011 Bitwise-OR
  
    101 comparision
  
    100 Bitwise-XOR
  

• output is 32-bit ALU_result.

• If the ALU_result is zero, a ZERO FLAG is set.

CONTROL.v

Here we are designing a control module for the processor using Verilog. It takes opcode, funct3, and funct7 inputs and produces ALU control signals and a register write control signal as outputs. Where Alu_control : This output port provides a 3-bit control signal to the ALU Regwrite_control : This output port indicates whether the instruction being executed requires writing to a register i.e ‘1’ for write , ’0’ for no write

We are executing whenever any of the input changes and, If the opcode is equal to 7’b0110011 then regwrite_control is set to 1 , indicating that the result of the operation should be written back to register

Depending upon values of funct3 and funct7 function codes, we are setting the alu_control signal to perform different operations like ADD, SUB, OR, AND, XOR, Comp.

DATAPATH.v

• Instantiating the register file , ALU module

Testbench.sv file

• This is the testbench code for ALU Processor.

• Firstly will initialize the Processor name say here it is "PROCESSOR.v", then inside the module clock, reset are declared as reg and zero as flag variable declared as wire.

• Instantiating the processor where all the input, output, reg, wire are specified.

• Next the simulation data are dumped,reset is set for 1 initially , later to 0.

• Clock is initialized to zero, then generation of clock where for every 20 time units clock is inverted.

• Then termination of the simulation takes place, so, after 300 time units have passed, the simulation will end.

github code link:

https://github.com/sumanthbs17/RISC-V_Processor

EDA Playground link

https://edaplayground.com/x/DHHP

output waveform

addition

• adding 8 and 9 , getting result as 17.

Subtraction

• Subtraction 25 with 24 , getting result as 1.

XOR Operation

XOR of 100010, 100011 is 1

OR Operation

OR of 10100, 10101 is 10101

And Operation

AND of 10100, 10101 is 10100

Comparision Operation

comparing 38 and 39,

38 is lesser than 39