Levels of Representation

Instructions

RISCV instructions are each 1 word = 4 bytes = 32bits

Registers in RISC -V

Symbolic Name	Number	Usage
zero	0	Hard-wired zero
ra	1	Return address
sp	2	Stack pointer
gp	3	Global pointer
tp	4	Thread pointer
t0	5	Temporary / alternative link register
t1 - t2	6 - 7	Temporaries
s0/fp	8	Saved registers/Frame pointer
s1	9	Saved register
a0-a1	10-11	Functional arguments/Return values
a2-a7	12-17	Functional arguments
s2-s11	18-27	Saved registers
t3-t6	28-31	Temporaries

• Zero: This register is hardwired to the value 0 and cannot be modified.
• x1-x31: These registers are general-purpose registers, with some having specific names to indicate their intended usage, such as:
• ra: Return address register, used for storing the return address in function calls.
• sp: Stack pointer register, used for managing the stack.
• gp: Global pointer register, used for accessing global data.
• tp: Thread pointer register, used for thread-local storage.
• s0-s1: Saved registers, used for preserving values across function calls.
• t0-t2: Temporary registers, used for holding intermediate values during calculations.
• a0-a7: : Argument registers, used for passing function arguments.
• s2-s11: Saved registers, used for preserving values across function calls.
• t3-t6: Additional temporary registers.

Base Instruction Format

There are 4 core instruction formats (R/I/S/U), all are fixed 32 bit length and aligned to 4byte boundary in memory.

• Every assembly language code is represented as patterns of 32 0's and 1's
• All instructions are of same size because of regularity
• Ideally we can have 1 instruction type, but some need more or less registers, so different types

R - Type

3 register operands

• 2 source registers rs1, rs2
• 1 destination register rd

Other Fields

• opcode, funct7, funct3

The function (7 bits and 3 bits respectively) with opcode tells computer what operation to perform.

R Format Example

(Assembly code)

add $a1, $a2, $a3

add x5, x6, x7

(Field values in decimal)

funct7	rs2	rs1	funct3	rd	opcode
0	7	6	0	5	51

(Field values in binary)

funct7	rs2	rs1	funct3	rd	opcode
0000000	00111	00110	000	00101	0110011
7 bits	5 bits	5 bits	3 bits	5 bits	7 bits

Now group these binary digits in set of 4 we get:

0000 0000 0111 0011 0000 0010 1011 0011

The equivalent machine code in hexadecimal format will be:

0x 007302B3

S-Type

3 register operands

• rs1 - base register
• rs2 - value to be stored to memory
• imm - 12 bit 2's complement immediate

Other Fields

• opcode, funct3

The function (3 bits) with opcode tells computer what operation to perform.

S Format Example

(Assembly code)

sw t2, -6(s3)

sw x7, -6(x19)

(Field values in decimal)

imm[11:5]	rs2	rs1	funct3	imm[4:0]	opcode
1111111	7	19	2	11010	35

(Field values in binary)

funct7	rs2	rs1	funct3	rd	opcode
1111111	00111	10011	010	11010	0100011
7 bits	5 bits	5 bits	3 bits	5 bits	7 bits

Now group these binary digits in set of 4 we get:

1111 1110 0111 1001 1010 1101 0010 0011

The equivalent machine code in hexadecimal format will be:

0x FE79AD23

I-Type

• Similar to R-format.
• The key difference between R-format and I-format is that the rs2 and funct7 of R-format is replaced by 12-bit signed immediate i.e., imm[11:0] in I-format.
• Imm[x] bits are always sign extended and generally packed towards leftmost available bits.

opcode (7 bits): uniquely specifies the instruction

rs1 (5 bits): specifies a register source operand

rd (5 bits): specifies destination register that receives result of computation

immediate (12): 12-bit immediate must be extended to 32 bits – always sign-extended to 32-bits before use in an arithmetic operation. We can represent 2^12 different immediates.

Example: addi x15, x1, -50 for an addi instruction we have opcode as 0010011 and func3 field as 000. X15 is destination register, x1 is source register and -50 represents immediate bits. Here -50 in binary form is 110010. Since it is signed number, the remaining bits of immediate field are sign extended(1 is inserted in remaining bit positions).

U-Type:

• Sometimes the immediate value may extend 12 bits then we cannot use I-format.
• So to deal with this a new format called U-format is introduced.

It has 20-bits immediate, one destination register rd and opcode. Used for two instructions

• LUI – Load Upper Immediate
• AUIPC – Add Upper Immediate to PC

Load and Store Instructions

RISCV32 is a load-store architecture, where only load and store instructions access memory and arithmetic instructions only operate on CPU registers.

• Loads are encoded in the I-type format and stores are S-type
• Load and store instructions transfer a value between the registers and memory
• The LW instruction loads a 32-bit value from memory into rd
• Stores copy the value in register rs2 to memory