RISC-V Addressing for Wide Immediates and Addresses

While it simplifies hardware to have all RISC-V instructions be 32 bits long, there are situations in which 32-bit or bigger constants or locations might be useful. The generic solution for big constants is presented in this section first, followed by the optimisations for instruction addresses utilised in branches.

Wide Immediate Operands

Constants might be larger or shorter, although they are usually small and fit within the 12-bit fields. Among the instructions in the RISC-V instruction set are To load a 20-bit constant into bits 12 through 31 of a register, use the load upper immediate (lui) function. Bit 31 copies occupy the leftmost 32 bits, whereas zeros occupy the rightmost 12 bits. For instance, this instruction makes it possible to generate a 32-bit constant using just two instructions. Lui employs the U-type instruction format since the other forms are unable to hold such a big constant.

Loading a 32-Bit Constant

Addressing in Branches

The SB-type RISC-V instruction format is used by the RISC-V branch instructions. Branch addresses in multiples of two from 4096 to 4094 can be represented using this format. For reasons that will become clear soon, you can only branch to even addresses. A 7-bit opcode, a 3-bit function code, two 5-bit register operands (rs1 and rs2), and a 12-bit address immediate make up the SB-type format. The address utilises a unique encoding that makes assembly more difficult but simplifies datapath construction.

The instruction bne x10, x11, 2000 // if x10 != x11, go to location 2000ten = 0111 1101 0000 could be assembled into this format

where the opcode for conditional branches is 1100111two and bne’s funct3 code is 001two.

Question

This sum resolves the branch address size issue by enabling the programme to have a maximum size of 264 and yet support conditional branches, But which register, then, is the question?

Solution