Processor design 5 - muneeb-mbytes/computerArchitectureCourse GitHub Wiki

Multi-cycle data path

The data path includes key resources like memory, register file, and ALU, which are utilized to maximize utilization and store intermediate results in registers for maximum utilization of resources.

For example, Instructions are stored in the instruction register (IR) when they are brought out of memory (Mem), while data is stored in the data register (DR) when it is read out.

Similarly, operands from register file(RF) are brought out into registers A and B, and the results of ALU operation are kept in register called Res. The task now requires the control of all these components.

Each register has a signal indicating when to write something into it, as all registers may not change their states in every cycle.

The multiplexer and ALU register file and memory are controlled, but new components like registers may alter the size or organization of the multiplexer.

Cycle-by-Cycle Breakdown of R-Type Instruction Execution

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  • The first cycle involves utilizing memory to retrieve the instruction and update the program counter.

  • In the next cycle, operands from the register file are read and brought into A and B. The addresses of the register file are provided by the instruction, with relevant fields being bit 21-25 for the second operand and bit 16-20 for the second operand. Both operations are done simultaneously within clock cycle number two.

  • The next instruction clock cycle will see the actual operation performed by the ALU, as described in a generic sense as A op B, guided by the function field of the instruction IR[5-0].

  • The final cycle involves transferring the result to the register file, using the address from bits 11 to 15, which corresponds to the destination register.

Cycle-by-Cycle Breakdown of SW Instruction Execution

  • The first cycle involves utilizing memory to retrieve the instruction and update the program counter.

  • The second cycle involves accessing two registers, one for address calculation and the other for writing values into memory, bringing the values into A and B.

  • In the next cycle , the address is calculated by adding the offset from bit 0 to 15 of the instruction with sign extension to A, temporarily stored in a register called result.

  • In the final cycle, memory is accessed using Res' contents as an address, and the data to be written into memory is B, and memory write is performed.

Cycle-by-Cycle Breakdown of LW Instruction Execution

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  • The first cycle involves utilizing memory to retrieve the instruction and update the program counter.
  • The second cycle involves reading one register from the register file, accessing only A, as the second address corresponds to the destination.
  • In the next cycle, the address is calculated by adding the offset from bit 0 to 15 of the instruction with sign extension to A, temporarily stored in the result(Res) register.
  • In the fourth cycle memory access is performed. The data is read from memory address is carried in Res and the data which is read is brought into DR.
  • The DR value is stored in the register file during the final cycle, with the address originating from the RD.

Cycle-by-Cycle Breakdown of BEQ Instruction Execution

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  • The first cycle involves utilizing memory to retrieve the instruction and update the program counter

  • The second cycle compares operands A and B, keeping the result ready for the target address. The ALU is free in this cycle, so it's used for comparison in the next cycle. The address of sx(IR{15-11}) is calculated but not immediately transferred to the PC. The condition is yet to be checked, and after checking, the address is either transferred or not transferred.

  • In last cycle , the ALU compares operands A and B from the register file, and if the condition is met, the new address is transferred to the PC.

Cycle-by-Cycle Breakdown of J Instruction Execution

  • The first cycle involves utilizing memory to retrieve the instruction and update the program counter.

  • In the second cycle, the address of the next instruction is composed by concatenating bits from PC and IR with a two-bit shift, then transferred to PC.