Processor Design ‐5 - muneeb-mbytes/computerArchitectureCourse GitHub Wiki

Multi-cycle data path

The data path includes key resources like memory, register file, and ALU, which are utilized to maximize utilization and store intermediate results in registers for maximum utilization of resources.

For example, Instructions are stored in the instruction register (IR) when they are brought out of memory (Mem), while data is stored in the data register (DR) when it is read out.

Similarly, operands from register file(RF) are brought out into registers A and B, and the results of ALU operation are kept in register called Res. The task now requires the control of all these components.

Each register has a signal indicating when to write something into it, as all registers may not change their states in every cycle.

The multiplexer and ALU register file and memory are controlled, but new components like registers may alter the size or organization of the multiplexer.

Cycle-by-Cycle Breakdown of R-Type Instruction Execution

• The first cycle involves utilizing memory to retrieve the instruction and update the program counter.

• In the next cycle, operands from the register file are read and brought into A and B. The addresses of the register file are provided by the instruction, with relevant fields being bit 21-25 for the second operand and bit 16-20 for the second operand. Both operations are done simultaneously within clock cycle number two.

• The next instruction clock cycle will see the actual operation performed by the ALU, as described in a generic sense as A op B, guided by the function field of the instruction IR[5-0].

• The final cycle involves transferring the result to the register file, using the address from bits 11 to 15, which corresponds to the destination register.

Cycle-by-Cycle Breakdown of SW Instruction Execution

• The first cycle involves utilizing memory to retrieve the instruction and update the program counter.

• The second cycle involves accessing two registers, one for address calculation and the other for writing values into memory, bringing the values into A and B.

• In the next cycle , the address is calculated by adding the offset from bit 0 to 15 of the instruction with sign extension to A, temporarily stored in a register called result.

• In the final cycle, memory is accessed using Res' contents as an address, and the data to be written into memory is B, and memory write is performed.

Cycle-by-Cycle Breakdown of LW Instruction Execution

• The first cycle involves utilizing memory to retrieve the instruction and update the program counter.
• The second cycle involves reading one register from the register file, accessing only A, as the second address corresponds to the destination.
• In the next cycle, the address is calculated by adding the offset from bit 0 to 15 of the instruction with sign extension to A, temporarily stored in the result(Res) register.
• In the fourth cycle memory access is performed. The data is read from memory address is carried in Res and the data which is read is brought into DR.
• The DR value is stored in the register file during the final cycle, with the address originating from the RD.

Cycle-by-Cycle Breakdown of BEQ Instruction Execution

• The first cycle involves utilizing memory to retrieve the instruction and update the program counter

• The second cycle compares operands A and B, keeping the result ready for the target address. The ALU is free in this cycle, so it's used for comparison in the next cycle. The address of sx(IR{15-11}) is calculated but not immediately transferred to the PC. The condition is yet to be checked, and after checking, the address is either transferred or not transferred.

• In last cycle , the ALU compares operands A and B from the register file, and if the condition is met, the new address is transferred to the PC.

Cycle-by-Cycle Breakdown of J Instruction Execution

• The first cycle involves utilizing memory to retrieve the instruction and update the program counter.

• In the second cycle, the address of the next instruction is composed by concatenating bits from PC and IR with a two-bit shift, then transferred to PC.

All the cycle sequences in together

• all the destination and main resources which are being used are retained
• for all in first cycle acess to memory is present and updation of PC is their
• overall skeleton of all the operations are shown above
• now finding the commanality and merging it and branching if required
• all different 5 sequences are to be done as single graph

After merging 1st cycle operations

• since first cycle is commom to all instruction and its carring out same activity, hence it is merged

Commom action is found for 2nd cycle (common decoding cycle)

• since all instructions dont require all oerations, their will be more enery consumption
• jump instructions operation is postponed to 3rd cycle

The repeating cycle

• this repeats like a chain
• the overall e is called instruction cycle
• the instructions cycle may require 4,5 or 3 as cases

Some improvements made

• lw and sw have one more cycle in common and can split after 3rd cycle
• by this one more control state is reduced

Control signals in multi-cycle DP

For each of the register, indicated a control signal,so, for PC PC write abbreviating as pw.

This is the IR write IW, DR write DW and then A and B have their AW and BW signals and Res write is ReW. So there are signals control signals which will indicate whether a particular register changes its state in a cycle or not and in which cycle the state is changed we will know from this flow chart.

Now we have also 1 2 3 4 5 and 6 multiplexers each one requires some controls so control for this multiplexer decides whether we are accessing instruction or data and accordingly the address comes from different sources.

This multiplexer decides whether we are writing into rt or rd, this decides what gets written into register file , we are calling it M2R memory to register or it is ALU out to the register.

The name of this signal is same Rdst we had earlier. this multiplexer is controlled by a signal called A source 1, this is controlled by A source 2 and we had earlier two registers and two multiplexers which were handling the next PC value; now it is the single multiplexer with three inputs and the control signal is labeled as p source or PC source.

The memory register file and ALU have their usual control signals same as what we had in the single cycle data path.

Now you would notice that there are many more control signals as compared to the single cycle data path we had. So I will not try to build the table exhaustively for all of these;

What happens if we will group the related control signals together and also identify the meaningful operation which we call as micro operations.

For example, PC plus p PC plus 4 going to PC will be considered as a micro operation; it is an understandable action within itself and it will affect some of the control signals in the data path.

So we will be grouping the signals according to our logical needs and then try to look at things group- wise so that will simplify the matter substantially.

A group of signals called PC group which are related to PC; program counter and its address.

So will build a table where will list micro operations which are related to PC and the signals which are related to PC.

So the signal you can see right now; one is Psrc the last multiplexer which is being controlled by this and the write signal for PC I have split into we have used two signals PWu and PWc; PC write unconditional and PC write conditional.

We would notice that in some micro operations like PC gets PC plus 4 we are writing it unconditionally whereas there was an operation where we are writing into PC with some condition.

So this state will generate a signal which will call as PWc conditional and a state like this or like this will generate a signal which we are going to call PWu unconditionally.

So the signal PW which is going here would be derived out of these two; But lets have a look on different micro operations and the signals which they imply.

So, for doing PC gets PC plus 4 I make PC PWu as 1, this then we need to care and the sourcewill select 1 so three things are going into this multiplexer if you recall is output of ALU directly, output of ALU through Res register then the address which is for the jump instruction.

Multicycle Operations and Control Signals - PC Group

Here, will write output of ALU directly into PC when we are doing PC plus 4 so we do not bring register into picture.

But the target address for a branch we are temporarily keeping into this we are not directly transferring to PC and therefore when we transfer to PC we will take from output of the register therefore both paths have been provided.

How the way z is going to be used, in the single cycle design we used z directly to control a multiplexer through AND gate so there was a signal coming from controller that was ANDed with z and we controlled a multiplexer.

This is next micro operation where we conditionally transfer an address to PC.

Here I activate this signal and do not activate this signal because source is 0 which means this value which is in Res is being taken and the third case is that the jump address goes to the PC.

So again this is unconditional, so PW u is 1, PW c is x and source is 2.

This is the address which is being formed for jump instruction, and in one of those cycles

So, in all these operations, notice that PC is the destination but the sources are different.

There are three different sources; and the multiplexer is selecting the sources.

This is 0 sorry this corresponds to 0 input of multiplexer, 1 input of multiplexer and 2 input of multiplexer this is all the things that have been connected in the data path so that takes care of what the value is being transferred and these two signals are taking care of whether this transfer is taking place conditionally or unconditionally and that default.

Hence, there are many control states where we are not changing the value of PC and there we need to keep both these as 0 and the value of P source does not matter.

The first one will call as PC increment, this is branch and this is jump and this we call no op or no operation. So just some names for convenience assigned to these.

Micro operations and control signals - Mem Group

The relevant signals here are memory write and read control signals, this I or D instruction or data this signal decides what is the source of address for the memory and these two signals decide where we keep the things which is coming out of the memory when we are reading from memory.

So, this controls writing into IR register, this controls writing into DR register and one operation is fetching the instruction.

So we are not writing here we are reading; it is an instruction and the multiplexer code for that is 0, the value which is being read is written in IR register so we keep this 1 keep that 0;

Next is getting data from memory so again we are reading we are not writing, it is data so that makes it 1, we are not storing to IR we are storing into DR so that is 1 and that is 0;

Next is writing into memory so now we make write as 1 and read as 0 once again it is data so I or D is 1 and we are not storing anything into IR or DR so both these are 0.

Multicycle Operations and Control Signals - Mem Group

There is some kind of redundancy in these signals.

It may appear that you may be you to derive one of these from others or one from one of these from more than one of others so there are yes many possibilities.

Some signals can be totally omitted, for example, IW and MR seem to be identical so we can make such observation and simplify the controller design.

So it is indeed possible but we will just limit at this and not get into those details.

Finally the default here is to keep a write read both signals low, also the register load signals low and then this does not really matter. Some convenient name for these; fetch, memory read, memory write and no operation.

Once fetch, it would mean that this is the operation we are performing and this is the set of values we have given to control signals of this particular group.

This is writing a signal RW register file write, Rdst this decides where the address comes from when you are writing; whether it is RT or RD, this tells where the data to be written is coming from whether it is coming from memory or from ALU and whether we are writing into A and B register.

So reading RS into A we make RW 0, Rdst don’t care and 2R don’t care, these Rdst and M2R will be relevant only when RW is 1 so when you are reading these do not matter we give a write signal to it and B does not require.

Similarly, reading into B is similar except that we write into we make BW as 1.

Now,it is writing into register file so will make the write signal 1, need to be defined Rdst so it will be 1 in this case, M2R is 0 and not modifying A and B.

This is writing DR into register file so again RW is 1 but this has a different value, Rdst is different because the address is coming from different points and also the values being written are different.

AW BW both are 0 and default is to keep RW 0 and to keep so we do not make any change in the state here so all write signals are kept 0.

Names are: rs2A, rt2B, res2rd, mem2rt and no operation.

ALU group

The signals involved include 'opc' which is a 2-bit signal derived from the opcode.

The ALU receives a 3-bit signal after considering opc and the function bits.

Additionally, we have control signals for the multiplexer: Asrc 1, Asrc2, and the signal governing the writing process into the result register (ReW).

So a micro operation which we saw earlier is appearing here also because doing PC gets PC plus 4 influences the PC group of signals as well as the ALU group of signals.

Asrc1 offers a selection between PC and A, while Asrc2 provides a choice between B, 4, and the offset for load/store or the offset for branch operations.

Asrc1 has 2 possibilities:

• 0 -> for PC

• 1 -> A

Asrc2 has 4 possibilities:

• 0 -> B

• 1 -> Store

• 2 -> load store offset

• 3 -> branch offset

ReW indicates whether we are writing into Res or not.

• 0 -> not writing into Res

• 1 -> writing into Res

opc has 3 possibilities

• 0 -> ALU controller ensures that ALU performs addition

• 1 -> Performs subtraction unconditionally

• 2 -> We look at function bits

The last case is the default case where there are don’t care terms where it does not matter what ALU does as long as the result is not written anywhere so we ensure that ReW is 0 and ALU may do Some operation which is considered as don’t care.

These micro operations can be represented as follows: PC increment, arithmetic, memory address, PC address, branch and no operation.

So all these micro operations have been put into appropriate states. Also, these states could be numbered: cs0 to cs9.

Relationship Between Control states and Control signals

• PC group ,MEM group, RF group, ALU group are the micro operations.

• cs0,cs1,cs2………………..cs9 are the control states.

• Cs0 performs following operations from each group.

• PC inc-PC increment in PC group.

• Fetch- fetching data from the Memory group.

• Nop-No operation in RF group.

• PC inc- PC increment in ALU group.

• In cs1 fetching the operands and calculating branch address.

• In cs2 state we are performing arithmetic operation.

• In cs3 the result value gets written in to the register file.

• Wherever we are not performing any operation that field is kept as nop.

• cs4 is the common state for load and store. Memory address is calculated in this state.

• By writing in to the memory group, cs5 completes the store operation.

• cs6 performs memory read operation.

• cs7 state performs the transfer of data from memory to register file.

• cs8 performs the branch operations In ALU group for comparison and PC group to change the state of pc.

• cs9 complete the jump instructions.

• All operations which perform in each state are the control signals, which go from controller to the data path.

Control state transitions

• For each state there is a next state. The next state is different depending upon the opcode value.

• From state cs0 it goes to cs1.

• R-class goes through cs0, cs1, cs3 and black to cs0.

• Store instruction starts with cs0 and go through cs1, cs4, cs5 and back to cs0.

• Load instruction goes through cs0, cs1, cs4,cs6,cs7and then cs0.

• Branch instruction goes through cs0,cs1 and cs8.

• Jump instruction goes through cs0,cs1,cs9 and back to cs0.