Problems with single cycle design - muneeb-mbytes/computerArchitectureCourse GitHub Wiki

Problems with single cycle design

Although the single-cycle design works, it's not efficient enough for modern use.

WHY?

1) Slowest instruction pulls down the clock frequency

  • In the single-cycle design, each instruction must take the same amount of time.
  • Certainly, the lengthiest route within the processor establishes the duration of the clock cycle.
  • This path is most likely a load instruction

Load instruction uses five functional units in series:

  • The instruction memory
  • The register file
  • The ALU
  • The data memory
  • The register file

Although CPI is one, the overall performance of a single cycle implementation is likely to be poor, since the clock cycle is too long.

What is CPI?

In computer architecture, CPI stands for "Clocks Per Instruction." 

It's a metric used to measure the average number of clock cycles required to execute each instruction in a program. 

A lower CPI indicates better performance, as it means instructions are being executed more efficiently.

2) Resource utilization is poor

  • Hardware resources remain idle during parts of the cycle when they're not needed for the current instruction being executed

3) There are some instructions which are impossible to be implemented in this manner

  • There are some instruction, which may necessarily require more than one cycles to take multiple steps

Consider this situation:

Reading from one address -> Perform operation -> Writing into another address

This is certainly cannot be done in a single cycle

Moving a block of data from one area in the memory to another area would require several reads & writes.

Using the single-cycle design with a fixed clock cycle has a significant downside, but it might be okay for this small set of instructions.

  • In the past, basic computers with straightforward instruction sets did utilize this implementation method.
  • However, if we attempted to incorporate a floating-point unit or a more intricate instruction set, this single-cycle design would not perform effectively.
  • We have to assume that the time it takes for the slowest instruction to finish determines the duration of each clock cycle.
  • So, trying methods that only speed up typical instructions without making the slowest ones faster won't help.