Part 2 - muneeb-mbytes/computerArchitectureCourse GitHub Wiki
Building blocks in processor design.
Building blocks refer to the fundamental components or functional units that collectively enable the processing of instructions and data. These building blocks work together to execute instructions, manage data flow, and control the operation of the processor.
There are two types:
- combinational elements
- sequential elements.
Circuits
Combinational circuits have output function of a current input with zero delay ideally.
Examples are all the gates, multiplexers, decoders, ALU, array multipliers (collection of adders and other logics put together).
Sequential circuits are those circuits where the output function depends on the present state and the next state inputs and uses memory elements to store the information with the respective delays.
Examples include flip flops, counters, registers, register files, memories (register files and memories are extension of flip-flops in two dimensions.) etc.
Clocked vs Unclocked circuit:
Sequential circuits are categorized into two main types: synchronous (clocked) and asynchronous (unclocked).
The main difference between the two is the timing of their signals:
1)Synchronous (clocked) circuits
Digital circuits that use clock signals to determine the timing of their operations. They are commonly used in digital systems to implement timers, counters, and memory elements.
Example of synchronous circuit:
D flip flop
A D flip-flop stores one bit of data. It captures the input (D) at the rising or falling edge of the clock signal (CLK), synchronizing data with the clock. Widely used in digital systems for storage, synchronization, and sequential logic operations.
Timing diagram:
2)Asynchronous (unclocked) circuits
Asynchronous circuits, also known as unclocked circuits, are digital circuits that do not depend on a clock signal to coordinate or synchronize the timing of their operations.
Example of Asynchronous circuit :
D latch:
One of the simplest examples of an asynchronous circuit is the SR latch. An SR latch is a fundamental building block in digital electronics, often used for memory storage or basic control applications. It consists of two cross-coupled NAND gates or NOR gates, forming a feedback loop that allows the circuit to latch into one of two stable states: SET (S = 1, R = 0) or RESET (S = 0, R = 1). When both inputs are set to 0 (S = 0, R = 0), the circuit maintains its current state. Asynchronous here implies that the transition between states can occur at any time, depending solely on the input signals, without the need for a clock signal to coordinate the timing of operations.
Timing diagram:
Edge triggerred
Clock and Timings
Consider two flip flops connected in series.There is combinational logic between two flip flops,which is consisting of some delay.Ideally data is read by first flipflop at first positive edge ,then transferred to second at second edge.Now depending upon what delay the combinational circuit have the output at the second edge is determined. So depending upon the delay we can have faster clock or slower clock or given a clock we can have a constraint on combinational circuit delay.Therefore this is the clock and timing relationship.
D signal should be stable some time before active edge of the clock this time is called the set up time .
D signal should be stable some time after active edge of the clock this time is called the hold time .
If this requirement are violated it can take previous or next value this may lead to metastablity condition.